Adapter for interconnecting single-ended and differential SCSI buses to prevent “busy” wired-or glitches from being passed from one bus to the other

A bus adapter for transferring a data signal and a corresponding control signal from a first bus to a second bus, said data signal having a plurality of HIGH and LOW states, said control signal indicating whether the corresponding DATA signal contains valid data information, said data signal and said control signal having a pre-selected timing relationship that can be altered during transfer over said first and second buses, said adapter operable to re-establish said timing relationship, said bus adapter comprising:

• A) a data latch that receives said data signal at a first input terminal and a clock signal having a series of HIGH and LOW states at a clock input terminal, said data latch passing said data signal on said input terminal to an output terminal in response to said clock signal being in one of said HIGH value states, said data latch passing the immediately prior state of said data signal in response to said clock signal being in said LOW state;
• and
• B) means coupled with said first bus and said data latch for providing a delayed version of said control signal received from said first bus to said clock input of the data latch as said clock signal.