Multiple resonant tunneling circuits for signed digit multivalued logic operations

Abstract

Circuits containing resonant tunneling devices are disclosed which offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. Multivalued logic circuits implemented with resonant tunneling devices can achieve increased speed and density over binary circuits and multiple-valued circuits implemented in conventional IC technologies since multiple binary bits are very efficiently processed by architectures which make use of devices with multiple negative transconductance regions. In one form of the invention, an adder for calculating the sum of two numbers represented by signed digit range-3 base-4 words is constructed from summation circuits 40 which add corresponding digits of input words X and Y to form digit sums Si, signed range-5 to signed range-3 converter circuits 42 which use multi-level folding circuits 64 connected by voltage dividers to decompose the digit sums into an interim sum and carry digit, and a second set of summation circuits 40 which add interim sum and carry digits to produce the digits of the result. Preferably, the sum is likewise represented by a signed digit range-3 base-4 word. Preferably, the multi-level folding circuits contain resonant tunneling transistors (e.g. bipolar transistors with multiple-peak resonant tunneling diodes 52 integrated into the emitter).

Dependencies are inferred from the claim text.