Digital filter, digital signal processing method, and communication apparatus

An X-time interpolation FIR type digital filter whose interpolation ratio is x (x is an integral number of 4 more) comprising:

• a delay unit of m stages (m is a natural FIG. 2 or more), in which serial data are inputted;
• m data distributors into which each of data of m bit outputted in parallel to each other from the respective stages of said delay unit are inputted, and which output the inputted data to each of x output terminals by time-sharing at a frequency which is x times the operating frequency of said delay unit;
• m*x multipliers which multiply each piece of data outputted from each of said x output terminals of said data distributors by digital coefficients;
• and
• x groups of adders which add to each other m pieces of data outputted in parallel at the same timing among the data outputted by time-sharing from said m*x multipliers.

An X-time interpolation FIR type digital filter, the digital filter coefficients of which is configured to be even-ordered and even-symmetrical, and the interpolation ratio of which is x (x is an integral number of 4 or more), comprising:

• a delay unit including delay elements composed of n stages (n is an even number of 2 or more), into which serial data are inputted;
• n/2 data distributors, into which two pieces of data outputted in parallel from a pair of delay elements located at symmetrical positions where the pair of delay elements overlap each other when a delay unit including of said delay elements of n stages is folded over into half centering around the point of connection of the (n/2)th delay element and (n+1/2)th delay element, are inputted, and which output the respective inputted data to x output terminals by time-sharing at a frequency which is x times the operating frequency of said delay unit;
• a coefficient holding circuit for holding coefficients equivalent to half at one side in said even-ordered and even-symmetrical digital filter coefficients;
• and
• a multiplier which multiplies each of the data outputted from said data distributors by digital filter coefficients corresponding thereto, respectively.

An X-time interpolation FIR type digital filter, the digital filter coefficients of which are configured to be even-ordered and even-symmetrical, and the interpolation ratio of which is x (x is an integral number of 4 or more), comprising:

• a delay unit including delay elements of n stages (n is an even number of 2 or more), into which serial data are inputted;
• n/2 data distributors in which the ratio of the number of inputs to that of outputs is 2:x;
• a coefficient holding circuit for holding coefficients equivalent to half at one side in said even-ordered and even-symmetrical digital filter coefficients;
• n*(x/2) multipliers which multiply each of the data outputted from said n/2 data distributors by digital filter coefficients corresponding thereto, respectively;
• and
• x/2 groups of adders which add to each other n pieces of data outputted in parallel at the same time among the data outputted by time-sharing from said n *(x/2) multipliers, and
• wherein two pieces of data outputted in parallel from a pair of delay elements located at symmetrical positions where the pair of delay elements overlap each other when a delay unit including said delay elements of n stages is folded over into half centering around the point of connection of the (n/2)th delay element and (n+1/2)th delay element, are inputted into each of said n/2 data distributors, and one piece of the data which is inputted into said data distributor is outputted by time-sharing one after another from the first output terminal toward the xth output terminal at a frequency which is x times the operating frequency of said delay unit, and the other inputted data is outputted one after another from the xth output terminal toward the first output terminal at a frequency which is x times the operating frequency of said delay unit.

An X-time interpolation FIR type digital filter, the digital filter coefficients of which are configured to be even-ordered and even-symmetrical, the number of taps of which is k (k is an even number) and the interpolation ratio of which is x (x is an integral number of 4 or more), comprising:

• a multiplexing circuit for multiplexing the first and second series of data, which are inputted in parallel in synchronization with the first clock, alternately in synchronization with the second clock of the frequency which is higher by two times than that of said first clock;
• a delay unit including delay elements of 2*(k/x) stages operating in synchronization with said second clock;
• k/x data distributors into which two pieces of data outputted in parallel to each other from a pair of delay elements located at the symmetrical positions where the pair of delay elements overlap each other when said delay unit including said 2*(k/x) delay elements is folded over into half centering around the point of connection of the (n/2)th delay element and (n+1/2)th delay element, are inputted, and which distribute the respective inputted data to two output terminals by time-sharing at the frequency which is higher by two times than that of said second clock;
• a coefficient holding circuit for holding only the coefficients equivalent to half at one side in said even-ordered and even-symmetrical digital filter coefficients;
• 2*(k/x) multipliers which multiply the respective data outputted from said output terminals of said data distributors by digital filter coefficients corresponding thereto, respectively;
• and
• a plurality of adders which perform additions with respect to the data outputted from the respective multipliers so that the independence of said first series and second series of data is maintained.

An X-time interpolation FIR type digital filter, the digital filter coefficients of which are configured to be even-ordered and even-symmetrical, the number of taps of which is k (k is an even number) and the interpolation ratio of which is x (x is an integral number of 4 or more), comprising:

• a multiplexing circuit for multiplexing the first series and second series of data, which are inputted in parallel to each other in synchronization with the first clock, alternately in synchronization with the second clock of a frequency higher by two times than that of said first clock;
• a delay unit including 2*(k/x) delay elements operating in synchronization with said second clock;
• k/x data distributors into which two pieces of data outputted in parallel to each other from a pair of delay elements located at the symmetrical positions where the pair of delay elements overlap each other when said delay unit is folded over into half centering around the point of connection of the n/2th delay element and (n+1/2)th delay element are inputted, and which distribute the respective inputted data to two output terminals by time-sharing at a frequency which is higher by two times than that of said second clock;
• a first coefficient holding circuit for holding coefficients equivalent to half at one side, which are in the digital filter coefficients used for processing said first series of data, of said even-ordered and even-symmetrical digital filter coefficients;
• a second coefficient holding circuit for holding coefficients equivalent to half at one side, which are in the digital filter coefficients used for processing said second series of data, of said even-ordered and even-symmetrical digital filter coefficients;
• a digital filter coefficient selecting circuit for selectively outputting either one of the digital filter coefficients held by said first coefficient holding circuit and the digital filter coefficients held by said second coefficient holding circuit, in synchronization with a clock of a frequency higher by two times than that of said second clock;
• 2*(k/x) multipliers for multiplexing the respective data outputted from said output terminals of said data distributors by digital filter coefficients;
• and
• a plurality of adders for performing additions so that the independence of said first series and second series of data is maintained with respect to the data outputted from the respective multipliers.

An X-time interpolation FIR type digital filter, the digital filter coefficients of which is configured to be even-ordered and even-symmetrical, the number of taps of which is k (k is an even number) and the interpolation ratio of which is x (x is an integral number of 4 or more), comprising:

• a multiplexing circuit for multiplexing the first series and second series of data, which are inputted in parallel to each other in synchronization with the first clock, alternately in synchronization with the second clock of a frequency higher by two times than that of said first clock;
• a delay unit of 2*(k/x) stages operating in synchronization with said second clock;
• k/x data distributors, into which two pieces of data outputted in parallel to each other from a pair of delay elements located at the symmetrical positions where the pair of delay elements overlap each other when said delay unit is folded over into half centering around the point of connection of the (n/2)th delay element and (n+1/2)th delay element, are inputted, and which distribute the respective inputted data to two output terminals by time-sharing at a frequency which is higher by two times than that of said second clock;
• a coefficient holding circuit for holding coefficients equivalent to half at one side in said even-ordered and even-symmetrical digital filter coefficients;
• 2*(k/x) multipliers which multiply each of the data outputted from said output terminals of said data distributors by digital filter coefficients corresponding thereto, respectively;
• a plurality of adders which perform additions with respect to the data outputted from the respective multipliers so that the independence of said first series and second series of data is maintained;
• and
• a frequency-variable clock generator being a clock generator for generating said first clock or said second clock, which is able to vary the frequency of clocks generated.

A digital signal processing method, for achieving a digital signal process substantially expressed by a transmission function H(z) of the following expression (1), in which a FIR type digital filter configured so as to have an even-ordered and even-symmetrical tap construction is used, by performing a digital signal process expressed by the respective transmission functions H(z) of the following expressions (2), (3), (4), and (5) by time-sharing;

• Expression (1)
• H(z)=h1+h2z-1+h3z-2+h4z-3+h5z-4+h6z-5+h7z-6+h8z-7+h9z-8+h10z-9+h11z-10+h12z-11+h13z-12+h14z-13+h15z-14+h16z-15+h17z-16+h18z-17+h19z-18+h20z-19+h21z-20+h22z-21+h23z-22+h24z-23+h25z-24+h26z-25+h27z-26+h28z-27+h29z-28+h30z-29+h31z-30+h32z-31
• Expression (2)
• H(z)=h1+h5z-4+h9z-8+h13z-12+h17z-16+h21z-20+h25z-24+h29z-28
• Expression (3)
• H(z)=h2z-1+h6z-5+h10z-9+h14z-13+h18z-17+h22z-21+h26z-25+h30z-29
• Expression (4)
• H(z)=h3z-2+h7z-6+h11z-10+h15z-14+h19z-18+h23z-22+h27z-26+h31z-30
• Expression (5)
• H(z)=h4z-3+h8z-7+h12z-11+h16z-15+h20z-19+h24z-23+h28z-27+h32z-31
• where, in expressions (1), (2), (3), (4), and (5), h1 through h32 mean, respectively, digital filter coefficients, z-1 through z-31 mean the first-ordered delay through the thirty-first-ordered delay.

A digital signal processing method, for achieving a digital signal process substantially expressed by a transmission function H(z) of the following expression (1), in which a FIR type digital filter configured so as to have an even-ordered and even-symmetrical tap construction is used, by performing a digital signal process expressed by the respective transmission functions H(z) of the following expressions (6), (7), (8), and (9) by time-sharing;

• Expression (1)
• H(z)=h1+h2z-1+h3z-2+h4z-3+h5z-4+h6z-5+h7z-6+h8z-7+h9z-8+h10z-9+h11z-10+h12z-11+h13z-12+h14z-13+h15z-14+h16z-15+h17z-16+h18z-17+h19z-18+h20z-19+h21z-20+h22z-21+h23z-22+h24z-23+h25z-24+h26z-25+h27z-26+h28z-27+h29z-28+h30z-29+h31z-30+h32z-31
• Expression (6)
• H(z)=h1+h5z-4+h9z-8+h13z-12+h16z-16+h12z-20+h8z-24+h4z-28
• Expression (7)
• H(z)=h2z-1+h6z-5+h10z-9+h14z-13+h15z-17+h11z-21+h7z-25+h3z-29
• Expression (8)
• H(z)=h3z-2+h7z-6+h11z-10+h15z-14+h14z-18+h10z-22+h6z-26+h2z-30
• Expression (9)
• H(z)=h4z-3+h8z-7+h12z-11+h16z-15+h13z-19+h9z-23+h5z-27+h1z-31
• where, in expression (1) and expressions (6), (7), (8), and (9), h1 through h32 mean digital filter coefficients, z-1 through z-31 mean the first-ordered delay through the thirty-first-ordered delay.

A digital signal processing method, for performing a digital signal process substantially expressed by a transmission function Hi(z) of the following expression (11), in which a FIR type digital filter configured so as to have an even-ordered and even-symmetrical tap construction is used, and a digital signal process substantially expressed by a transmission function Hq(z) of the following expression (12), in which a FIR type digital filter configured so as to have an even-ordered and even-symmetrical tap construction is used, respectively in parallel to each other, comprising the steps of:

• performing the respective digital signal processes, which are expressed by the respective transmission functions H(z) of expressions (13) and (14) shown in the following State 1, in parallel to each other;
• performing the respective digital signal processes, which are expressed by the respective transmission functions H(z) of expressions (15) and (16) shown in the following State 2, in parallel to each other;
• performing the respective digital signal processes, which are expressed by the respective transmission functions H(z) of expressions (17) and (18) shown in the following State 3, in parallel to each other;
• and
• performing the respective digital signal processes, which are expressed by the respective transmission functions H(z) of expressions (19) and (20) shown in the following State 4, in parallel to each other.
• Expression (11)
• Hi(z)=h1+h2zi-1+h3zi-2+h4zi-3+h5zi-4+h6zi-5+h7zi-6+h8zi-7+h9zi-8+h10zi-9+h11zi10+h12zi-11+h13zi-12+h14zi-13+h15zi-14+h16zi-15+h17zi-16+h18zi-17+h19zi-18+h20zi-19+h21zi-20+h22zi-21+h23zi-22+h24zi-23+h25zi-24+h26zi-25+h27zi-26+h28zi-27+h29zi-28+h30zi-29+h31zi-30+h32zi-31
• Expression (12)
• Hq(z)=h1+h2zq-1+h3zq-2+h4zq-3+h5zq-4+h6zq-5+h7zq-6+h8zq-7+h9zq-8+h10zq-9+h11zq-10+h12zq-11+h13zq-12+h14zq-13+h15zq-14+h16zq-15+h17zq-16+h18zq-17+h19zq-18+h20zq-19+h21zq-20+h22zq-21+h23zq-22+h24zq-23+h25zq-24+h26zq-25+h27zq-26+h28zq-27+h29zq-28+h30zq-29+h31zq-30+h32zq-31
• (State 1)
• Hi(z)=h1+h5zi-4+h9zi-8+h13zi-12+h16zi-16+h12zi-20+h8zi-24+h4zi-28 (13)
• Hq(z)=h3zq-2+h7zq-6+h11zq-10+h15zq-14+h14zq-18+h10zq-22+h6zq-26+h2zq-30 (14)
• (State 2)
• Hi(z)=h2zi-1+h6zi-5+h10zi-9+h14zi-13+h15zi-17+h11zi-21+h7zi-25+h3zi-29 (15)
• Hq(z)=h4zq-3+h8zq-7+h12zq-11+h16zq-15+h13zq-19+h9zq-23+h5zq-27+h1zq-31 (16)
• (State 3)
• Hi(z)=h3zi-2+h7zi-6+h11zi-10+h15zi-14+h14zi-18+h10zi-22+h6zi-26+h2zi-30 (17)
• Hq(z)=h1+h5zq-4+h9zq-8+h13zq-12+h16zq-16+h12zq-20+h8zq-24+h4zq-28 (18)
• (State 4)
• Hi(z)=h4zi-3+h8zi-7+h12zi-11+h16zi-15+h13zi-19+h9zi-23+h5zi-27+h1zi-31 (19)
• Hq(z)=h2zq-1+h6zq-5+h10zq-9+h14zq-13+h15zq-17+h11zq-21+h7zq-25+h3zq-29 (20)
• where, in expressions (11) through (20), h1 through h32 mean digital filter coefficients, and z-1 through z-31 mean the first-ordered delay through the thirty-first-ordred delay.