Clock control signal and output enable signal generator in semiconductor memory device

A clock control signal and output enable signal generating circuit of a semiconductor memory device that comprises a plurality of first registers for storing a plurality of data output signals, a plurality of second registers for storing the output signals of the first registers in response to a clock control signal, and a plurality of logic gates and output drivers for outputting the output signals of the plurality of the second registers in response to an output enable signal, the circuit comprising:

• a first control signal and clock control signal generating circuit for generating a first control signal and a clock control signal for controlling a shift from a high impedance to a low impedance after 1 cycle of a read command in a pipelined operation, and for generating a high level of the clock control signal in a flow through operation;
• a second control signal generating circuit for generating a second control signal to control a shift from a low impedance to a high impedance in a following cycle after a read command is input sequentially before one of a deselect command and a write command in a pipeline operation, and to generate a low level of the second control signal in a flow through operation;
• a write pass through signal generating circuit for generating a write pass through signal in a read command cycle, in case the read command is sequentially input after a write command in a pipeline operation;
• a third control signal generating circuit for generating a third control signal for detecting a shift from a low impedance of low level to a high impedance in an operation of double cycle deselect function, and for generating the third control signal in one of a deselect command cycle and a write command cycle when respectively a deselect command and a write command are input sequentially after a read command in an operation of single cycle deselect function;
• and
• an output enable signal generating circuit for generating an output enable signal in response to an output enable control signal in a flow through operation, for generating the output enable signal of high level in response to the second control signal and a signal inverted from the first control signal, and for generating the output enable signal of low level in response to one of the second control signal and the third control signal in a pipeline operation.