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US 6,192,004 B1Granted
Semiconductor integrated circuit
AssigneeFujitsu Limited
InventorsTadao Aikawa, Yasuharu Sato
Life of this patent
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AssigneeFujitsu Limited
InventorsTadao Aikawa, Yasuharu Sato
Estimating the term…
A clock pulse generator generates a plurality of clock pulses which has different phases during one cycle of a reference clock signal supplied from the exterior. A timing setting circuit sets a latency, which is a number of clock cycles from a start of a read operation to an output of read data, at a number which is divisible by one n-th (n=2, 3, 4 . . . ) of a cycle of the reference clock signal and outputs latency information according to the set latency. An output controlling pulse switching circuit respectively outputs each of the clock pulses as a predetermined output controlling pulse in accordance with the latency information. In other words, a plurality of the output controlling pulses are switched according to the latency information. In synchronization with each of the output controlling pulses, a data outputting circuit sequentially and respectively converts parallel data, read from a plurality of memory cells stored with data, into serial data and respectively outputs the converted serial data during the predetermined period according to the latency. No matter what timing of the reference clock signal the latency might be set at, therefore, the serial data can be reliably outputted without switching the parallel data. The data are outputted at high speed because the parallel data need not be switched.
A semiconductor integrated circuit comprising:
A semiconductor integrated circuit comprising:
A semiconductor integrated circuit comprising:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: for memories with random access ports…
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time…:…
Term ended 27 Apr 2020 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for outputting data signals read from memory cells at a plurality of times during one cycle of a clock signal and, more particularly, to a technology for outputting the data signals at high speed.
2. Description of the Related Art
The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:
FIG. 1 is a block diagram showing an output controlling unit in the DDR-SDRAM of the prior art;
FIG. 2 is a circuit diagram showing a clock pulse generator of the prior art;
A semiconductor integrated circuit of the invention will be described in connection with its one embodiment with reference to the accompanying drawings.
The semiconductor integrated circuit of this embodiment is formed as a DDR-SDRAM of 64 Mbits, for example, on a silicon substrate by using the CMOS process technology. The DDR-SDRAM includes a peripheral circuit unit and a memory core unit same as the ordinary semiconductor memory. An output controlling unit and an input controlling unit, as will be described hereinafter, are formed in the peripheral circuit unit. A memory cell array having a plurality of memory cells and a sense amplifier and the like are formed in the memory core unit.
The same circuits as those described in the prior art are designated by the identical reference numerals, and their description will be omitted. Likewise, the same signals as those described in the prior art are designated by the identical numerals.