Semiconductor memory device using a relatively low-speed clock frequency and capable of latching a row address and a column address with one clock signal and performing a page operation

A semiconductor memory device comprising:

• a memory cell array having a plurality of memory cells each for retaining data;
• a plurality of word lines selectively activated by a row address signal;
• a plurality of bit lines each being selected by a column address signal;
• sense amplifiers for amplifying data read out onto the bit lines connected thereto;
• a row address latch circuit for latching the row address signal in response to a row address latch signal;
• a column address latch circuit for latching the column address signal in response to a column address latch signal;
• and
• timing control means responsive to a clock signal for controlling timings of internal operations of the semiconductor memory device, the timing control means generating:
• the row address latch signal by using, as a trigger, a first edge of the clock signal;
• generating a sense amplifier enable signal for activating the sense amplifiers, in response to the first edge, after a lapse of a given delay time;
• generating the column address latch signal by using, as a trigger, a second edge of the clock signal occurring after the first edge;
• and generating a bit line precharge signal for precharging the bits lines, in response to the second edge, after a lapse of a given delay time.