Memory device with command buffer

A computer system, comprising:

• a microprocessor adapted to issue a plurality of memory requests;
• a memory controller coupled to the microprocessor and adapted to receive the memory requests and generate memory access commands based on the memory requests, the memory access commands including a block write command;
• a memory device coupled to the memory controller and adapted to receive the memory access commands, the memory device including:
• a memory array arranged in rows and columns;
• an external clock terminal adapted to receive an external clock signal, the external clock signal having at least a first cycle and a second cycle, the first cycle including a first edge and the second cycle including a second edge;
• control logic coupled to the memory array and the external clock terminal and adapted to write to a first plurality of the columns in a specified row during the first and second cycles in response to the block write command, wherein the control logic is further adapted to suspend the external clock signal to suppress the second edge of the second cycle while writing to the first plurality of the columns.

A method for accessing a memory device arranged in rows and columns, comprising:

• receiving an external clock signal, the external clock signal having at least a first cycle and a second cycle, the first cycle including a first edge and the second cycle including a second edge;
• writing to a first plurality of columns in a specified row during the first and second cycles;
• and
• suspending the external clock signal to suppress the second edge of the second cycle while writing to the first plurality of the columns.

A memory device, comprising:

• means for storing data arranged in rows and columns;
• means for receiving an external clock signal, the external clock signal having at least a first cycle and a second cycle, the first cycle including a first edge and the second cycle including a second edge;
• means for writing to a first plurality of columns in a specified row during the first and second cycles;
• and
• means for suspending the external clock signal to suppress the second edge of the second cycle while writing to the first plurality of the columns.