Integrated weak write test mode (WWWTM)

A memory cell write driver comprising a first driver gate including:

• a first driver gate output for providing an output signal whose value is based on an input data value to be applied at the memory cell;
• a first supply node for powering the first driver gate, wherein the strength of the first driver gate output signal corresponds to the amount of power transferred between the first supply node and the first driver gate;
• and
• a controllably variable resistive path connected to the first supply node for controlling the amount of power transferred between the first supply node and the first driver gate, wherein the controllably variable resistive path has first and second settings, the first setting having a larger resistance than the second setting, wherein the first setting causes the driver gate to provide a weak write output signal, and the second setting causes the driver gate to provide a normal write output signal for writing the data value into a healthy memory cell.

A method of performing a weak write test on a memory cell with a write driver having an output that is operably connected to the memory cell, comprising the steps of:

• setting the write driver to a first mode so that a normal write output signal for writing to a healthy cell is generated at the output;
• writing a first value into the memory cell from the output;
• setting the write driver to a second mode so that a weak write signal is generated at the output;
• weak writing a second value from the output to the memory cell;
• and
• reading the value in the memory cell, wherein the memory cell is assessed as being defective if its value is not the first value.