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US 6,192,000 B1Granted
Semiconductor memory device having decreased layout area and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorHaruki Toda
Life of this patent
Estimating the term…
Abstract
A word line driving circuit drives four word lines in response to a signal supplied from a main row decoder through a main word line and in response to a word line driving voltage supplied from a sub-row decoder. When the word line driving circuit is not selected by the main word line, a first reset circuit allows each word line to be short-circuited. When the word line driving circuit is selected by the main word line, second to fifth reset circuits allow the non-selected word line to bear a ground potential by using a signal of the selected word line.
Claims25
A semiconductor memory device, comprising:
- a plurality of word lines connected to memory cells;
- a first word line selecting circuit for generating a signal for selecting a group of word lines from the plural word lines;
- a second word line selecting circuit for supplying a driving voltage to a single word line included in the selected group of word lines in accordance with the signal supplied from said first word line selecting circuit;
- a first reset circuit connected to the group of word lines for short-circuiting each word line of the group of word lines when the signal is not generated by the first word line selecting circuit;
- and
- a second reset circuit connected to each word line in the group of word lines, said second reset circuit driven in accordance with the potential of the word line selected by the second word line selecting circuit, and configured to set non-selected word line to a predetermined potential.
3 more elements
A semiconductor memory device, comprising:
- a plurality of word lines connected to memory cells;
- a first word line selecting circuit for generating a signal for selecting a group of word lines from the plural word lines;
- a plurality of first transistors of a first conductivity type having a first end of a current path connected to each word line included in the group of word lines, the signal generated from said first word line selecting circuit being supplied to a gate of each of said first transistors;
- a second word line selecting circuit connected to a second end of the current path of said first transistors for forming a driving voltage for driving one word line included in the selected group of word lines, the driving voltage being supplied to the second end of the current path of each of said first transistors;
- a first reset circuit connected to said group of word lines for short-circuiting each word line of the group of word lines when the signal is not supplied from the first word line selecting circuit;
- and
- a second reset circuit connected to each word line in the group of word lines, said second reset circuit driven in accordance with the potential of the word line selected by the second word line selecting circuit, and configured to set non-selected word lines to a predetermined potential.
4 more elements
A method of manufacturing a semiconductor memory device, comprising the steps of:
- forming a wiring trench within an insulating film, an etching resistant first film being formed on that portion of said insulating film which is positioned around the wiring trench;
- forming a resist film having an opening on said first film, said opening being sized larger than a contact hole formed in said wiring trench;
- etching said insulating film with said resist film and said first film as a mask to form said contact hole communicating with the wiring trench, said contact hole being formed in a region of logical multiplication between said wiring trench and said opening;
- depositing a conductive film on the entire surface to fill the wiring trench and the contact hole with said conductive film;
- and
- removing that portion of the conductive film which is positioned on the insulating film to allow the conductive film to remain within the wiring trench and the contact hole.
3 more elements
A method of manufacturing a semiconductor memory device, comprising the steps of:
- forming a first film on an insulating film, said first film being lower in its etching rate than said insulating film;
- etching said first film to form a pattern conforming with a wiring trench;
- forming a resist film having an opening on the first film, said opening being sized larger than the width of said pattern;
- etching said insulating film with the first film and the resist film used as a mask to form a contact hole, said contact hole being formed in a region of the logical multiplication between the pattern of the first film and the opening of the resist film;
- removing said resist film;
- etching the insulating film with the pattern of the first film used as a mask to form said wiring trench communicating with said contact hole, the depth of said wiring trench being smaller than that of said contact hole;
- depositing a conductive film on the entire surface to allow said conductive film to fill the wiring trench and the contact hole;
- and
- removing that portion of the conductive film which is positioned on the insulating film to allow the conductive film to remain within the wiring trench and the contact hole.
6 more elements
Dependencies are inferred from the claim text.