Semiconductor memory device with reduced power consumption
AssigneeFujitsu Limited
InventorsWaichirou Fujieda, Shinya Fujioka, Tadao Aikawa
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Abstract
A semiconductor memory device using hierarchical word decoding for word selection includes memory-cell areas, each of which is provided for a corresponding one of column blocks. The semiconductor memory device further includes sub-word lines provided for each one of the column blocks and extending over a corresponding one of the memory-cell areas, and sub-word decoders provided on either side of a given one of the memory-cell areas to select one of the sub-word lines only with respect to the given one of the memory-cell areas.
Claims27
A semiconductor memory device having a hierarchical word line structure, comprising:
- a plurality of column blocks, each including a plurality of sub-word lines which are connected to memory cells and separated at each boundary between said column blocks;
- and
- sub-word decoders disposed on both sides of each of said column blocks to select the sub-word lines, wherein the sub-word decoders disposed between neighboring column blocks are coupled to the sub-word lines of only one of said neighboring column blocks.
A semiconductor memory device comprising:
- a plurality of main-word lines;
- a main-word decoder selecting one of said plurality of main-word lines;
- a plurality of column blocks, each including a plurality of sub-word lines which are connected to memory cells and separated at each boundary between said column blocks;
- and
- sub-word decoders, disposed on both sides of each of said column blocks, for coupling said main-word lines to the sub-word lines, wherein the sub-word decoders disposed between neighboring column blocks are coupled to the sub-word lines of only one of said neighboring column blocks.
A semiconductor memory device having a hierarchical word line structure, comprising:
- sub-word lines disposed in first and second column blocks;
- sub-word decoders shared by said first and second column blocks and coupled to said sub-word lines;
- first and second sense-amplifier blocks provided for said first and second column blocks, respectively;
- and
- a column-block-selection circuit selecting the sub-word decoders and activating both of said first and second sense-amplifier blocks in response to a column block address signal designating either one of said first and second column blocks.
A semiconductor memory device comprising:
- a plurality of main-word lines;
- a main-word decoder which selects one of said plurality of main-word lines;
- a plurality of column blocks arranged in a column direction and including memory cells;
- sub-word lines provided for each one of said plurality of main-word lines;
- sub-word decoders shared by at least two of said plurality of column blocks and coupled to said sub-word lines in said at least two of said plurality of column blocks;
- sense-amplifier blocks provided for each one of said plurality of column blocks;
- a column-block-selection circuit activating said sense-amplifier blocks in said at least two of said plurality of column blocks in response to a column block address signal designating either one of said at least two of said plurality of column blocks.
A semiconductor memory device having a hierarchical word line structure, comprising:
- sub-word lines provided for each one of column blocks;
- sub-word decoders shared by at least some column blocks and coupled to said sub-word lines in said at least some column blocks;
- sense-amplifier blocks provided for each of said column blocks;
- and
- a column-block-selection circuit selectively activating said sense-amplifier blocks only with respect to column blocks which share a selected one of said sub-word decoders.
Dependencies are inferred from the claim text.