Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel.

A memory comprising:

• a plurality of columns of memory storage units, each memory storage unit comprising one or more memory cells, each column having a column address;
• an odd column decoder block for decoding an address signal and selecting an odd column (that is, a column having an odd column address);
• an even column decoder block for decoding an address signal and selecting an even column (that is, a column having an even column address);
• a counter for receiving one or more bits of a starting column address of a burst operation, and for providing a count during the burst operation, the count comprising one or more bits of a first column address of a first column to be accessed in the burst operation;
• and
• a first circuit for receiving one or more bits of the count and generating one or more bits of a second column address of a second column to be accessed in the burst operation in parallel with the first column;
• wherein in at least one burst operation the one or more bits of the first column address are different from the one or more bits of the second column address, and one of the odd and even column decoder blocks is to decode an address signal comprising the one or more bits of the first column address, and, in parallel, the other one of the odd and even column decoder blocks is to decode an address signal comprising the one or more bits of the second column address, so that the odd and even column decoder blocks select in parallel an odd column and an even column at non-consecutive column addresses or at consecutive column addresses starting at an odd address boundary.