Sharing signal lines in a memory device
AssigneeMicron Technology, Inc.
InventorsBrian W. Huber, Todd A. Dauenbaugh
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory array and at least two sets of row decoders to drive row lines in the memory array. Select lines (such as row select lines) carry signals to select one or more decoders in one of the two sets of decoders. At least some of the select lines are shared between the two sets of row decoders to decrease the space needed to route signal lines in the memory array.
Claims28
A memory device, comprising:
- a memory array;
- at least two sets of decoders adapted to drive control lines in the memory array;
- and
- select lines coupled to the decoders, and providing first select signals to the first set of decoders and second select signals to the second set of decoders, at least some of the select lines alternating between carrying the first and second select signals.
A memory device, comprising:
- a memory array;
- at least two sets of row decoders to drive row lines in the memory array;
- and
- select lines carrying signals to select one or more decoders in one of the two sets of decoders, wherein at least some of the select lines are shared between the two sets of row decoders.
A memory device, comprising:
- a plurality of memory array strips each including a portion of a memory array;
- at least two sets of decoders positioned between two memory array strips;
- and
- control lines routed to the at least two sets of decoders to control selection of the decoders, at least some of the control lines being shared between the at least two sets of decoders.
An integrated circuit device, comprising:
- a plurality of memory cells;
- first control circuits to drive control lines to a first set of memory cells;
- second control circuits to drive control lines to a second set of memory cells;
- and
- select lines coupled to both the first and second control circuits alternately carrying select signals associated with the first and second control circuits.
A method of controlling access of memory cells in an integrated circuit device, comprising:
- providing signal lines to at least two sets of decoders that drive control lines to the memory cells;
- alternately driving select signals associated with one of the two sets of decoders on the signal lines;
- and
- selecting one or more of the decoders in one of the two sets with the select signals.
A circuit, comprising:
- a decoder driving row select signals onto shared signal lines for alternately controlling selection of a first set and a second set of row decoders;
- and
- a multiplexer to select first row select signals or second row select signals for communicating on the shared signal lines.
A memory array, comprising:
- a first and a second row decoder capable of driving control lines in the memory array;
- and
- a select line capable of carrying a signal to select at least one of the first row decoder and the second row decoder, wherein the select line is shared by the first and second row decoder.
A memory device, comprising:
- a memory array;
- a first and a second decoder capable of driving control lines in the memory array;
- and
- an address decoder coupled to the first and second decoder by at least one select line, wherein the at least one select line is shared by the first and second decoder.
The memory device 23, wherein the first decoder and second decoder comprise a set of decoders adapted to drive control lines in the memory array.
Dependencies are inferred from the claim text.