First in first out memory circuit
OwnerKenjiro Matobainventor
Life of this patent
Estimating the term…
Abstract
A first-in, first-out memory circuit includes first and second memory part respectively having first and second address locations each of which has a first word length, a write address counter outputting a write address signal and a memory part selection signal to the first and second memory parts in response to a word length selection signal, and a memory part enable circuit which is coupled between the write address counter and the first and second memory parts and receives the memory part selection signal. The memory circuit also includes a data bus which is applied with the input data and which includes a first data bus having the first word length and a second data bus having the first word length, and a data input part which is coupled between the data bus and the first and second memory parts.
Claims10
A first-in, first-out memory circuit for storing data according to a data length of an input data, said memory circuit comprising:
- a first memory part which has a plurality of first address locations each having a first word length and each storing a data therein and which has a first input port for receiving the input data and a first output port for outputting the data stored in the first address locations, wherein the data stored in the first address locations are read out to the first output port in response to an enable signal and a read address signal;
- a second memory part which has a plurality of second address locations each having the first word length and each storing a data therein, and which has a second input port for receiving the input data and a second output port for outputting the data stored in the second address locations, wherein each of the second address locations corresponds to the respective first address locations, and wherein the data stored in the second address locations are read out to the second output port in response to the enable signal and the read address signal;
- a read address counter which outputs the read address signal designating the first and second address locations and an output data selection signal in response to a word length selection signal, wherein the word length selection signal is a first voltage which designates a first data mode when the data length of the input data is not greater than the first word length, and wherein the word length selection signal is a second voltage which designates a second data mode when the data length of the input data is greater than the first word length;
- a data bus which includes a first data bus having the first word length and a second data bus having the first word length;
- and
- a data output part, coupled between the first and second output ports and said data bus, which transfers the data on the first output port and the data on the second output port to the second data bus in the first data mode, and which transfers the data on the first and second output ports to the first and second data buses respectively in the second data mode.
Dependencies are inferred from the claim text.