Semiconductor integrated circuit device having stabilizing capacitors connected between power lines of main amplifiers

A semiconductor integrated circuit device comprising:

• a memory cell array which includes a plurality of word lines, a plurality of bit lines and a plurality of dynamic memory cells located at the intersections of said word lines and bit lines;
• a plurality of sense amplifiers which are connected to said bit lines and adapted to amplify signals read out of said dynamic memory cells;
• common data lines provided commonly to said bit lines;
• a column switch which transfers the signals on said bit lines to said common data lines selectively;
• main amplifiers which amplify the signals placed on said common data lines;
• a pair of power lines which are connected to said main amplifiers to supply a power voltage;
• and
• a stabilizing circuit including capacitance elements connected between said power lines,
• said dynamic memory cells each including a storage capacitor and a selecting MOSFET, with one electrode of said storage capacitor being connected to a corresponding bit line through the source-drain path of said selecting MOSFET and another electrode corresponding to a plate electrode of a certain shape formed on the semiconductor substrate, and with said one electrode of said capacitance element being formed in a plate electrode forming process to have said certain shape.

A semiconductor integrated circuit device comprising:

• a memory cell array which includes a plurality of word lines, a plurality of bit lines and a plurality of dynamic memory cells located at the intersections of said word lines and bit lines;
• a plurality of sense amplifiers which are connected to said bit lines and adapted to amplify signals read out of said dynamic memory cells;
• common data lines provided commonly to said bit lines;
• a column switch which transfers the signals on said bit lines to said common data lines selectively;
• main amplifiers which amplify the signals placed on said common data lines;
• a pair of power lines which are connected to said main amplifiers to supply a power voltage;
• and
• a voltage stabilizing circuit connected between said power lines,
• said dynamic memory cells each including a storage capacitor and a selecting MOSFET, with one electrode of said storage capacitor being connected to a corresponding bit line through the source-drain path of said selecting MOSFET and another electrode corresponding to a plate electrode of a certain shape formed on the semiconductor substrate,
• said voltage stabilizing circuit including a first and second capacitance elements which are connected in series between said power lines and a third and fourth capacitance elements which are connected in parallel to said first and second capacitance elements, respectively, with said first, second, third and fourth capacitance elements each having a first electrode of said certain shape.

A semiconductor integrated circuit device comprising:

• a memory cell array which includes a plurality of word lines, a plurality of bit lines and a plurality of dynamic memory cells located at the intersections of said word lines and bit lines;
• a plurality of sense amplifiers which are connected to said bit lines and adapted to amplify signals read out of said dynamic memory cells;
• common data lines provided commonly to said sense amplifiers;
• a column switch which transfers the signals produced by said sense amplifiers to said common data lines selectively;
• main amplifiers which amplify the signals transmitted to said common data lines;
• a pair of power lines which are connected to said main amplifiers to supply a pair of power voltages;
• and
• a first and second stabilizing capacitance elements connected in series between said power lines, with said first and second stabilizing capacitance elements being applied on the connection node thereof an intermediate voltage of said power voltages.

A semiconductor integrated circuit device comprising:

• a memory cell array which includes a plurality of word lines, a plurality of bit lines and a plurality of dynamic memory cells located at the intersections of said word lines and bit lines;
• a plurality of sense amplifiers which are connected to said bit lines and adapted to amplify signals read out of said dynamic memory cells;
• common data lines provided commonly to said sense amplifiers;
• a column switch which transfers the signals produced by said sense amplifiers to said common data lines selectively;
• main amplifiers which amplify the signals transmitted to said common data lines;
• a pair of power lines which are connected to said main amplifiers to supply a pair of power voltages;
• and
• stabilizing capacitance elements connected between said power lines,
• wherein storage capacitance elements which constitute said dynamic memory cells each have a pair of confronting electrodes having the same shape as that of a pair of confronting electrodes of said stabilizing capacitance elements.

A semiconductor integrated circuit device comprising:

• a memory cell array which includes a plurality of word lines, a plurality of bit lines and a plurality of dynamic memory cells located at the intersections of said word lines and bit lines;
• a plurality of sense amplifiers which are connected to said bit lines and adapted to amplify signals read out of said dynamic memory cells;
• common data lines provided commonly to said sense amplifiers;
• main amplifiers which amplify the signals transmitted to said common data lines;
• a data output circuit which releases data produced by said main amplifiers;
• a pair of first power lines which are connected to said main amplifiers to supply a pair of power voltages;
• a pair of second power lines which are connected to said data output circuit to supply a pair of power voltages;
• a first stabilizing capacitance element connected between said first power lines;
• and
• a second stabilizing capacitance element connected between said second power lines,
• wherein storage capacitance elements which constitute said dynamic memory cells each have a pair of confronting electrodes having the same shape as that of a pair of confronting electrodes of each of said first and second stabilizing capacitance elements.