Floating bitline timer allowing a shared equalizer DRAM sense amplifier
AssigneeInternational Business Machines Corporation
InventorJohn K. DeBrosse
Life of this patent
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Abstract
A method and structure for a dynamic random access memory chip includes memory element arrays having bitlines, a sense amplifier shared by the arrays. The sense amplifier includes multiplexors connected to the bitlines, an equalizer circuit connected to the multiplexors and a timer circuit connecting first bitlines to the sense amplifier a time period after second bitlines are sensed by the sense amplifier, wherein the time period is less than the active phase of the row cycle.
Claims20
A dynamic random access memory chip comprising:
- memory element arrays having bitlines;
- a sense amplifier shared by said arrays, said sense amplifier including multiplexors connected to said bitlines, and an equalizer circuit connected to said multiplexors;
- and
- a timer circuit connecting first bitlines of said bitlines to said sense amplifier a time period after second bitlines of said bitlines are sensed by said amplifier, wherein said time period is less than an active phase of a row cycle of said bitlines.
A timer circuit for use in memory element arrays having bitlines, at least one sense amplifier being shared by said arrays, said sense amplifier including multiplexors connected to said bitlines, and an equalizer circuit connected to said multiplexors,
- said timer circuit connecting first bitlines of said bitlines to said sense amplifier a time period after second bitlines of said bitlines are sensed by said sense amplifier, wherein said time period is less than an active phase of a row cycle of said bitlines.
A method of equalizing bitlines in memory element arrays having a sense amplifier shared by said arrays, said sense amplifier including multiplexors connected to said bitlines, and an equalizer circuit connected to said multiplexors, said method comprising:
- beginning a sensing of first bitlines of said bitlines;
- allowing a time period to elapse;
- and
- connecting second bitlines of said bitlines to said sense amplifier,
- said time period being less than an active phase of a row cycle of said bitlines.
Dependencies are inferred from the claim text.