US 6,191,987 B1 · Semiconductor memory test circuit

Abstract

A semiconductor memory test circuit comprises a current mirror circuit including a reference side current path composed of a series connection of alternating p channel transistors and n channel transistors and an output side current path composed of a series connection of alternating p channel transistors and n channel transistors, an output signal for electrode of paired memory cells and a balance potential output signal for sense amplifier, required for a semiconductor memory test, being derived from the output side current path. The current mirror circuit includes a first output side current path and a second output side current path, the balance output for sense amplifier is derived from an output of the first output side current path and the output signal for electrode of paired memory cells is derived from an output of the second output side current path.

Claims9

Dependent claims

A semiconductor memory test circuit comprising a current mirror circuit including a reference side current path composed of a series connection of alternating P channel transistors and N channel transistors and an output side current path composed of a series connection of alternating P channel transistors and N channel transistors, an output signal for an electrode of paired memory cells and a balance potential output signal for a sense amplifier, required for a semiconductor memory test, being derived from said output side current path,

wherein said current mirror circuit includes a first output side current path and a second output side current path, the balance output for said sense amplifier is derived from an output of said first output side current path and the output signal for said electrode of paired memory cells is derived from an output of said second output side current path.

A semiconductor memory test circuit comprising:

a first current mirror circuit including a first N channel transistor provided between a first power source terminal and a first node, a second N channel transistor provided between said first power source terminal and a second node and a third N channel transistor provided between said first power source terminal and a third node, gates of said first, second and third N channel transistors being connected commonly;
a second current mirror circuit including a first P channel transistor provided between a second power source terminal and said first node, a second P channel transistor provided between said second power source terminal and said second node and a third P channel transistor provided between said second power source terminal and said third node, gates of said first, second and third P channel transistors being connected commonly;
a balance potential output terminal for a sense amplifier, connected to said second node;
and
an output terminal for electrode of paired memory cells, connected to said third node.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor memory test circuit

Life of this patent

Semiconductor memory test circuit

Life of this patent

Abstract

Claims9