Semiconductor memory
AssigneesHitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
InventorsGoro Kitsukawa, Toshitsugu Ueda, Manabu Ishimatsu, Michihiro Mishima
Life of this patent
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Abstract
There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.
Claims4
A semiconductor memory comprising:
- a plurality of memory cells which are disposed two-dimensionally in the word line and bit line directions in a memory cell array, said plurality of memory cells are composed of a large number of normal memory cells and a small number of redundant memory cells;
- and peripheral circuits having word drivers and sense amplifiers on the outside of said memory cell array which are capable of switching an operation to said redundant memory cell when said normal memory cell is defective,
- wherein said redundant memory cells are disposed approximately at the center in said word line and bit line directions, a layout unit of said word drivers and sense amplifiers connected to said redundant memory cell is substantially equal to what layouts for the redundant memory cell and for the normal memory cell are combined and is substantially equal to the layout unit of said normal memory cell and a control input of said word driver or said sense amplifier is replaced among those for the normal and redundant ones.
Dependencies are inferred from the claim text.