Address comparing for non-precharged redundancy address matching with redundancy disable mode

An integrated circuit 1, comprising:

• a plurality of address lines carrying addresses;
• a plurality of primary circuit elements selectable by the addresses;
• a redundant circuit element;
• a match circuit including a set of programmable storage devices capable of being set to a combination of states representing one of the addresses so as to produce a match signal for substituting the redundant circuit element for a certain one of the primary circuit elements in response to the one address;
• and
• a redundancy disable circuit coupled to the match circuit and responsive to a redundancy control signal for disabling the substitution of the redundant circuit element for the certain primary circuit element;
• wherein the integrated circuit is a dynamic random access memory comprising an array of memory cells arranged in rows and columns, and wherein the primary circuit elements comprise rows of memory cells.

An integrated circuit, comprising:

• a plurality of address lines carrying addresses;
• a plurality of primary circuit elements selectable by the addresses;
• a redundant circuit element;
• a match circuit including a set of programmable storage devices capable of being set to a combination of states representing one of the addresses so as to produce a match signal for substituting the redundant circuit element for a certain one of the primary circuit elements in response to the one address;
• and
• a redundancy disable circuit coupled to the match circuit and responsive to a redundancy control signal for disabling the substitution of the redundant circuit element for the certain primary circuit element;
• wherein the integrated circuit is a dynamic random access memory comprising an array of memory cells arranged in rows and columns, and wherein the primary circuit elements comprise columns of memory cells.

An integrated circuit, comprising:

• a plurality of address lines carrying addresses;
• a plurality of primary circuit elements selectable by the addresses;
• a redundant circuit element;
• a match circuit including a set of programmable storage devices capable of being set to a combination of states representing one of the addresses so as to produce a match signal for substituting the redundant circuit element for a certain one of the primary circuit elements in response to the one address;
• and
• a redundancy disable circuit coupled to the match circuit and responsive to a redundancy control signal for disabling the substitution of the redundant circuit element for the certain primary circuit element;
• wherein the match circuit includes a plurality of sub-match circuits each including a subset of the programmable storage devices.

An integrated circuit, comprising:

• a plurality of address lines carrying addresses;
• a plurality of primary circuit elements selectable by the addresses;
• a redundant circuit element;
• a match circuit including a set of programmable storage devices capable of being set to a combination of states representing one of the addresses so as to produce a match signal for substituting the redundant circuit element for a certain one of the primary circuit elements in response to the one address;
• and
• a redundancy disable circuit coupled to the match circuit and responsive to a redundancy control signal for disabling the substitution of the redundant circuit element for the certain primary circuit element;
• wherein the integrated circuit has a plurality of redundant circuit elements and a plurality of match circuits each including a set of programmable storage devices capable of being set to a combination of states representing a different one of the addresses for substituting each redundant circuit element for a different one of the primary circuit elements in response to the different addresses.

An integrated circuit, comprising:

• a plurality of address lines carrying addresses;
• a plurality of primary circuit elements selectable by the addresses;
• a redundant circuit element;
• a match circuit including a set of programmable storage devices capable of being set to a combination of states representing one of the addresses so as to produce a match signal for substituting the redundant circuit element for a certain one of the primary circuit elements in response to the one address;
• a redundancy disable circuit coupled to the match circuit and responsive to a redundancy control signal for disabling the substitution of the redundant circuit element for the certain primary circuit element;
• and
• a programmable master storage device coupled to the match circuit and capable of being set to a condition indicating that at least one of the primary circuit elements is being replaced by one of the redundant circuit elements.

An integrated circuit, comprising:

• a plurality of address lines carrying addresses;
• a plurality of primary circuit elements selectable by the addresses;
• a redundant circuit element;
• a match circuit including a set of programmable storage devices capable of being set to a combination of states representing one of the addresses so as to produce a match signal for substituting the redundant circuit element for a certain one of the primary circuit elements in response to the one address;
• and
• a redundancy disable circuit coupled to the match circuit and responsive to a redundancy control signal for disabling the substitution of the redundant circuit element for the certain primary circuit element;
• wherein the programmable storage devices have two states.

An integrated circuit, comprising:

• a plurality of address lines carrying addresses;
• a plurality of primary circuit elements selectable by the addresses;
• a redundant circuit element;
• a match circuit including a set of programmable storage devices capable of being set to a combination of states representing one of the addresses so as to produce a match signal for substituting the redundant circuit element for a certain one of the primary circuit elements in response to the one address;
• and
• a redundancy disable circuit coupled to the match circuit and responsive to a redundancy control signal for disabling the substitution of the redundant circuit element for the certain primary circuit element;
• wherein the redundancy control signal is controllable from external to the integrated circuit.

An integrated circuit, comprising:

• a plurality of address lines carrying addresses;
• a plurality of primary circuit elements selectable by the addresses;
• a redundant circuit element;
• a match circuit including a set of programmable storage devices capable of being set to a combination of states representing one of the addresses so as to produce a match signal for substituting the redundant circuit element for a certain one of the primary circuit elements in response to the one address;
• and
• a redundancy disable circuit coupled to the match circuit and responsive to a redundancy control signal for disabling the substitution of the redundant circuit element for the certain primary circuit element;
• wherein the substitution of the redundant circuit element for the certain primary circuit element is disabled permanently after receipt of the redundancy control signal.

An integrated circuit receiving n address bits and comprising:

• primary circuit element means being selectable by the n address bits;
• and redundant circuit element means each comprising:
• a plurality of sub-match circuit means, each including programmable two-state storage means being programmable to a programmed state wherein at least one of the two-state storage means is in a first of the two states and the rest of the two state storage means are in a second of the two states, so as to substitute at least one of the redundant circuit element means for at least one of the primary circuit element means, and wherein each sub-match circuit means is responsive to at least one of a plurality of addresses to activate a sub-match signal when the at least one of the addresses corresponds to the at least one of the two-state storage means in the first state;
• redundancy disable circuit means in each sub-match circuit means responsive to a redundancy control signal being in a first state to deactivate an activated sub-match signal, and
• a match circuit means coupled to the plurality of sub-match circuit means for activating a match signal in response to all of the sub-match signals being active, wherein the activated match signal is used to disable a primary circuit element means from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element means to be selected by the corresponding binary value of the n address bits.

An integrated circuit receiving n address bits and comprising:

• primary circuit element means being selectable by the n address bits;
• and redundant circuit element means each comprising:
• a plurality of sub-match circuit means, each including programmable two-state storage means being programmable to a programmed state wherein at least one of the two-state storage means is in a first of the two states and the rest of the two state storage means are in a second of the two states, so as to substitute at least one of the redundant circuit element means for at least one of the primary circuit element means, and wherein each sub-match circuit means is responsive to at least one of a plurality of addresses to activate a sub-match signal when the at least one of the addresses corresponds to the at least one of the two-state storage means in the first state;
• redundancy disable circuit means in each sub-match circuit means responsive to a redundancy control signal being in a first state to deactivate an activated sub-match signal, and
• a match circuit means coupled to the plurality of sub-match circuit means for activating a match signal in response to all of the sub-match signals being active, wherein the activated match signal is used to disable a primary circuit element means from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element means to be selected by the corresponding binary value of the n address bits;
• wherein the integrated circuit is a dynamic random access memory means comprising an array of memory cell means arranged in rows and columns.

A method of replacing primary circuit elements with redundant circuit elements in an integrated circuit receiving n address bits, wherein the primary circuit elements are selectable by binary values of the n address bits, the method comprising the steps of:

• programming a plurality of programmable storage devices to a programmed state specifying one combination of the n address bits;
• producing a match signal in response to the one combination of address bits;
• accessing one of the redundant circuit elements in response to the match signal;
• activating a redundancy control signal;
• disabling the access of the one redundant circuit element in response to the control signal.

A method of operating an integrated circuit having a plurality of primary circuit elements individually accessible by a plurality of addresses, at least one redundant circuit element, and a match circuit having a plurality of programmable storage devices settable to one of the addresses, the method comprising:

• applying the one address to the integrated circuit;
• producing a match signal in response to the one address;
• accessing the redundant circuit element in response to the match signal;
• applying a redundancy disable signal to the match circuit;
• and
• while the redundancy disable signal and the one address are both applied, accessing one of the primary circuit elements instead of the redundant circuit element.

A method of operating an integrated circuit having a plurality of primary circuit elements individually accessible by a plurality of addresses, at least one redundant circuit element, and a match circuit having a plurality of programmable storage devices settable to one of the addresses, the method comprising:

• applying the one address to the integrated circuit;
• producing a match signal in response to the one address;
• accessing the redundant circuit element in response to the match signal:
• applying a redundancy disable signal to the match circuit:
• and while the redundancy disable signal and the one address are both applied, accessing one of the primary circuit elements instead of the redundant circuit element, wherein the addresses each have a plurality of portions, and further comprising producing a plurality of sub-match signals in response to the individual portions of the one address;
• and
• combining the sub-match signals so as to produce the match signal.