Semiconductor memory device with reduced precharging time for bit lines
AssigneeNEC Corporation
InventorMasaki Uekubo
Life of this patent
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Abstract
A semiconductor memory device having a bit line which is precharged quickly is disclosed. According to the presenti invention, a semiconductor memory device includes a bit line which is connected to a memory cell, a first precharging circuit which precharges said bit line during a first time period, and a second precharging circuit which precharges said bit line during a second time period, wherein said first time period being longer than said second time period.
Claims9
A semiconductor memory device, comprising:
- a bit line which is connected to a memory cell;
- a first precharging circuit which precharges said bit line during a first time period;
- and
- a second precharging circuit which precharges said bit line during a second time period,
- said first time period being longer than said second time period.
In a semiconductor memory device provided with a current sensing data read means which selects a specified memory cell from a memory cell array and generates an on-current in it after raising a bit line potential to a desired level necessary for sensing, at the time of precharging in which a precharging signal is activated in the state where a sense amplifier enabling signal is activated, and an output voltage obtained by converting the current using a current to voltage conversion means provided with a feedback means which inputs the change in the current by feedback, is compared in a differential amplifier means with an output voltage of a reference voltage generation means having the identical configuration with said current to voltage conversion means, to decide the data storage condition of the memory cell during sensing period where the precharging signal is deactivated, the semiconductor memory device characterized in that said semiconductor memory device includes a dummy current to voltage conversion means which controls a dummy memory cell having identical configuration with a memory cell equivalent to one column component of said memory cell array and a transfer transistor which supplies charge to the cell with a dummy feedback means which inputs the output potential of the transistor by feedback, and increases or decreases charge supply to said dummy memory cell as well as generates a specified voltage in response to the change in said charge supply from a load transistor of said transfer transistor, and is further provided with a charge supply control means which controls to shorten the time required for said charge supply to said current to voltage conversion means with said dummy current to voltage conversion means.
Dependencies are inferred from the claim text.