Sense circuit for a multi-level flash memory cell

A sense circuit for a multi-level flash memory cell having a drain, a source and a program gate, the sense circuit comprising:

• a first means for supplying multi-steps voltage;
• a reference voltage;
• and
• a second means for sensing data stored in said memory cell, wherein the data are sensed by sequentially comparing voltages detected from the drain of said memory cell and said reference voltage under a drain voltage is applied to said drain, a ground voltage is applied to said source and said multi-steps voltage are sequentially applied to the program gate, and converting said compared results.

A sense circuit for a multi-level flash memory cell having associated therewith a reference cell, the sense circuit comprising:

• a control signal generator configured to receive a sense amplifier enable signal and output a first plurality of voltage control signals, a clock signal having a constant period and a second plurality of control pulses;
• a control voltage generator configured to receive said first plurality of voltage control signals, said clock signal and said sense amplifier enable signal, and output a read-out signal having a variable voltage level which depends on said first plurality of voltage control signals, and a reference voltage;
• and
• a sense amplifier configured to receive said second plurality of control pulses, first data from a drain of said multi-level flash memory cell and second data from a drain of said reference cell and output a result of a comparison of said first data with said second data, in binary form.

In a flash memory device comprising at least one multi-level flash memory cell having associated therewith a reference cell, the improvement comprising a sense circuit including:

• a control signal generator configured to receive a sense amplifier enable signal and output a first plurality of voltage control signals, a clock signal having a constant period and a second plurality of control pulses;
• a control voltage generator configured to receive said first plurality of voltage control signals, said clock signal and said sense amplifier enable signal, and output a read-out signal having a variable voltage level which depends on said first plurality of voltage control signals, and a reference voltage;
• and
• a sense amplifier configured to receive said second plurality of control pulses, first data from a drain of said multi-level flash memory cell and second data from a drain of said reference cell and output a result of a comparison of said first data with said second data, in binary form.

A sense circuit for a multi-level flash memory cell having associated therewith a reference cell, the multi-level flash memory cell and the reference cell each having a program gate, a source and a drain, the sense circuit comprising:

• a first circuit configured to output a read-out signal having a variable voltage level and a reference voltage;
• and
• a second circuit configured to sense data stored in said flash memory cell by comparing voltage outputs at drains of said flash memory cell and said reference cell, and then output said data in digital form, wherein
• the read-out signal is connected to a program gate of the flash memory cell so as to successively apply a plurality of voltage levels thereto;
• the reference voltage is connected to a program gate of reference memory cell;
• the sources of the flash memory cell and the reference cell are grounded;
• and
• a comparison of the voltage outputs is made for each of said plurality of voltage levels to read the data stored in said flash memory cell.