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US 6,191,976 B1Granted
Flash memory margin mode enhancements
AssigneeTexas Instruments Incorporated
InventorsMichael C. Smayling, Giulio G. Marotta, Giovanni Santin
Life of this patent
Estimating the term…
Abstract
FLASH Memory sense amplifier reference circuit with weighted dummy loads is used to balance and bias the sense amplifier during erasing, programming, and verification such that the resulting robust stored logic states can meet more stringent pass-fail verify “1” or verify “0” tests. Programming in this manner guarantees logic states which meet full operating temperature and full power supply tolerances requirements.
Claims4
A FLASH memory sense circuit comprising:
- a FLASH memory MOS transistor having source-drain path connected between a first sensing terminal and ground, said FLASH memory MOS transistor storing thereon a charge indicative of a digital state;
- a fixed load device connected between said first sensing node and a predetermined voltage;
- a dummy FLASH memory MOS transistor having source-drain path connected between a second sensing terminal and ground;
- a selectable load device connected between said second sensing terminal and said predetermined voltage, said selectable load providing a selectable resistance between said second sensing terminal and said predetermined voltage;
- and
- a sense amplifier connected to said first and second sensing terminals having an output indicative of which of said first or second sensing terminals has a greater voltage, wherein:
- said selectable load device consists of a plurality of dummy load MOS transistors, each having a source-drain path connected between said second sensing node and said predetermined voltage and a gate connected to receive respective select signals, said selectable load device providing said selectable resistance by predetermined combinations of said select signals turning ON said respective dummy load MOS transistors.
4 more elements
A method of operating FLASH memory comprising the steps of:
- disposing a series connection of a FLASH memory MOS transistor and a fixed load between a predetermined voltage and ground, thereby providing a voltage at an intermediate node therebetween;
- comparing said voltage at said intermediate node to a first reference voltage during normal reading of the FLASH memory;
- comparing said voltage at said intermediate node to a second reference voltage during verification of programming a “0” in said FLASH memory MOS transistor;
- and
- comparing said voltage at said intermediate node to a third reference voltage during verification of programming a “1” in said FLASH memory MOS transistor;
- disposing a first, second and third dummy load MOS transistors between said predetermined voltage and said second intermediate node, said first, second and third dummy load MOS transistors each having a channel width twice a channel width of said fixed load;
- disposing a dummy FLASH memory MOS transistor between said second intermediate node and ground, thereby providing a reference voltage at said second intermediate node;
- said step of generating said first reference voltage consists of supplying signals to gates of said first, second and third dummy load MOS transistors to cause said first and second dummy load MOS transistors to be ON and said third dummy load MOS transistor to be OFF;
- said step of generating said second reference voltage consists of supplying signals to gates of said first, second and third dummy load MOS transistors to cause said first, second and third dummy load MOS transistors to be ON;
- and
- said step of generating said third reference voltage consists of supplying signals to gates of said first, second and third dummy load MOS transistors to cause said first dummy load MOS transistor to be ON and said second and third dummy load MOS transistors to be OFF.
8 more elements
Dependencies are inferred from the claim text.