Mram cam
AssigneeMotorola, Inc.
InventorWilliam C. Moyer
Life of this patent
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Abstract
An integrated circuit (IC) magnetic random access memory (MRAM) content addressable memory (CAM) system has a CAM cell which includes a first data bit, a second data bit, and an equalization bit, all of which are MRAM cells. The CAM is written by first initializing the equalization bit using a current. The first and second data bits are written by currents that are flowing in different directions. After initializing the equalization bit, an input bit in one state indicates that the first and second data bits are written in first and second directions, respectively. The input bit in another state indicates that the first and second bits are written in the second and first directions, respectively.
Claims10
In an integrated circuit (IC) magnetic random access memory (MRAM) content addressable memory (CAM) system having at least one CAM cell consisting of:
- a first data bit, comprised of a first MRAM cell which is writeable in a first logic state in response to a coincidence of a word_write current and a first bit_write current provided in a first direction, and in a second logic state in response to a coincidence of said word_write current and said first bit_write current provided in a second direction;
- a second data bit, comprised of a second MRAM cell which is writeable in said first logic state in response to a coincidence of said word_write current and a second bit_write current provided in said first direction, and in said second logic state in response to a coincidence of said word_write current and said second bit_write current provided in said second direction;
- and
- an equalization bit, comprised of a third MRAM cell which is writeable in a first logic state in response to a coincidence of a word_write current and an equalization bit_write current provided in a first direction, and in a second logic state in response to a coincidence of said word_write current and said equalization bit_write current provided in a second direction;
- a method for writing said CAM cell, comprising the steps of:
- initializing said equalization bit by:
- providing said word_write current;
- providing said equalization bit_write current to said equalization MRAM cell in said first direction;
- and thereafter
- receiving an input bit having one of said first and second logic states;
- providing said word_write current;
- in response to receiving said input bit in said first logic state:
- providing said first bit_write current to said first MRAM cell in said first direction;
- and
- providing said second bit_write current to said second MRAM cell in said second direction;
- and
- in response to receiving said input bit in said second logic state:
- providing said first bit_write current to said first MRAM cell in said second direction;
- and
- providing said second bit_write current to said second MRAM cell in said first direction.
An integrated circuit (IC) magnetic random access memory (MRAM) content addressable memory (CAM) system having at least one CAM cell consisting of:
- a first data bit, comprised of a first MRAM cell which is writeable in a first logic state in response to a coincidence of a word_write current and a first bit_write current provided in a first direction, and in a second logic state in response to a coincidence of said word_write current and said first bit_write current provided in a second direction;
- a second data bit, comprised of a second MRAM cell which is writeable in said first logic state in response to a coincidence of said word_write current and a second bit_write current provided in said first direction, and in said second logic state in response to a coincidence of said word_write current and said second bit_write current provided in said second direction;
- an equalization bit, comprised of a third MRAM cell which is writeable in a first logic state in response to a coincidence of a word_write current and an equalization bit_write current provided in a first direction, and in a second logic state in response to a coincidence of said word_write current and said equalization bit_write current provided in a second direction;
- and
- a write control circuit comprising:
- a word_write current driver circuit which provides said word_write current;
- an equalization bit_write driver circuit which initially provides said first bit_write current to said equalization MRAM cell in said first direction;
- a first bit_write driver circuit which, in response to receiving an input bit in a first logic state, provides said first bit_write current to said first MRAM cell in said first direction, and, in response to receiving said input bit in a second logic state, provides said first bit_write current to said first MRAM cell in said second direction;
- and
- a second bit_write driver circuit which, in response to receiving said input bit in said first logic state, provides said second bit_write current to said first MRAM cell in said second direction, and, in response to receiving said input bit in said second logic state, provides said second bit_write current to said first MRAM cell in said first direction.
Dependencies are inferred from the claim text.