Ferroelectric memory device

A ferroelectric memory device for reading out a high level or low level corresponding to the direction of polarization of a ferroelectric film from a memory cell to a bit line, applying a reference potential from a dummy cell to a reference bit line which makes a complementary pair with the bit line and comparing the potential of the bit line with the reference potential of the reference bit line to sense and rewrite stored data, comprising:

• a plate line driving circuit for pulse-driving a plate line associated with a memory cell selected at the time of data readout;
• a dummy plate line driving circuit for pulse-driving a dummy plate line associated with a dummy cell connected to a reference bit line which makes a complementary pair with a bit line connected to the selected memory cell;
• a constant voltage generator for applying a power supply voltage to said plate line driving circuit and dummy plate line driving circuit, said constant voltage generator including a bandgap reference circuit, an operational amplifier supplied with an output voltage of said bandgap reference circuit at a non-inverting input terminal thereof, and a voltage dividing circuit for dividing the potential of the output terminal of said operational amplifier and supplying the divided potential to an inverting input terminal of said operational amplifier, and outputting a potential of the output terminal of said operational amplifier.

A ferroelectric memory device for reading out a high level or low level corresponding to the direction of polarization of a ferroelectric film from a memory cell to a bit line, applying a reference potential from a dummy cell to a reference bit line which makes a complementary pair with the bit line and comparing the potential of the bit line with the reference potential of the reference bit line to sense and rewrite stored data, comprising:

• a plate line driving circuit for fixedly driving a plate line associated with a memory cell selected;
• a dummy plate line driving circuit for fixedly driving a dummy plate line associated with a dummy cell connected to a reference bit line which makes a complementary pair with a bit line connected to the selected memory cell;
• and
• a constant voltage generator for applying a power supply voltage to said plate line driving circuit and dummy plate line driving circuit, said constant voltage generator including a bandgap reference circuit, an operational amplifier supplied with an output voltage of said bandgap reference circuit at a non-inverting input terminal thereof and a voltage dividing circuit for dividing the potential of the output terminal of said operational amplifier and supplying the divided potential to an inverting input terminal of said operational amplifier, and outputting a potential of the output terminal of said operational amplifier.

A ferroelectric memory device for reading out a high level or low level corresponding to the direction of polarization of a ferroelectric film from a memory cell to a bit line, applying a reference potential from a dummy cell to a reference bit line which makes a complementary pair with the bit line and comparing the potential of the bit line with the reference potential of the reference bit line to sense and rewrite stored data, comprising:

• a plate line driving circuit for pulse-driving a plate line associated with a memory cell selected at the time of data readout;
• a dummy plate line driving circuit for pulse-driving a dummy plate line associated with a dummy cell connected to a reference bit line which makes a complementary pair with a bit line connected to the selected memory cell;
• a constant voltage generator for applying a power supply voltage to said plate line driving circuit, said constant voltage generator including a first bandgap reference circuit, a first operational amplifier supplied with an output voltage of said first bandgap reference circuit at a non-inverting input terminal thereof, and a first voltage dividing circuit for dividing the potential of the output terminal of said first operational amplifier and supplying the divided potential to an inverting input terminal of said first operational amplifier, and supplying a potential of the output terminal of said first operational amplifier to said plate line driving circuit;
• and
• a variable voltage generating circuit for applying a power supply voltage to said dummy plate line driving circuit, said variable voltage generating circuit including a second bandgap reference circuit, a second operational amplifier supplied with an output voltage of said second bandgap reference circuit at a non-inverting input terminal thereof, and a second voltage dividing circuit for dividing the potential of the output terminal of said second operational amplifier into a plurality of potentials and selectively supplying one of the divided potentials to an inverting input terminal of said second operational amplifier, and supplying a potential of the output terminal of said second operational amplifier to said dummy plate line driving circuit.

A ferroelectric memory device for reading out a high level or low level corresponding to the direction of polarization of a ferroelectric film from a memory cell to a bit line, applying a reference potential from a dummy cell to a reference bit line which makes a complementary pair with the bit line and comparing the potential of the bit line with the reference potential of the reference bit line to sense and rewrite stored data, comprising:

• a plate line driving circuit for fixedly driving a plate line associated with a memory cell selected at the time of data readout;
• a dummy plate line driving circuit for fixedly driving a dummy plate line associated with a dummy cell connected to a reference bit line which makes a complementary pair with a bit line connected to the selected memory cell;
• a constant voltage generator for applying a power supply voltage to said plate line driving circuit, said constant voltage generator including a first bandgap reference circuit, a first operational amplifier supplied with an output voltage of said first bandgap reference circuit at a non-inverting input terminal thereof, and a first voltage dividing circuit for dividing the potential of the output terminal of said first operational amplifier and supplying the divided potential to an inverting input terminal of said first operational amplifier, and supplying a potential of the output terminal of said first operational amplifier to said plate line driving circuit;
• and
• a variable voltage generating circuit for applying a power supply voltage to said dummy plate line driving circuit, said variable voltage generating circuit including a second bandgap reference circuit, a second operational amplifier supplied with an output voltage of said second bandgap reference circuit at a non-inverting input terminal thereof, and a second voltage dividing circuit for dividing the potential of the output terminal of said second operational amplifier into a plurality of potentials and selectively supplying one of the divided potentials to an inverting input terminal of said second operational amplifier, and supplying a potential of the output terminal of said second operational amplifier to said dummy plate line driving circuit.

A ferroelectric memory device for reading out a high level or low level corresponding to the direction of polarization of a ferroelectric film from a memory cell to a bit line, applying a reference potential from a dummy cell to a reference bit line which makes a complementary pair with the bit line and comparing the potential of the bit line with the reference potential of the reference bit line to sense and rewrite stored data, comprising:

• a plate line driving circuit for pulse-driving a plate line associated with a memory cell selected at the time of data readout;
• a dummy plate line driving circuit for pulse-driving a dummy plate line associated with a dummy cell connected to a reference bit line which makes a complementary pair with a bit line connected to the selected memory cell;
• a constant voltage generator for applying a power supply voltage to said plate line driving circuit and said dummy plate line driving circuit,
• wherein said dummy cell includes:
• a selection transistor which has a current path connected at one end to the reference bit line, and a gate connected to a dummy word line;
• and a linear capacitor made of an MOS transistor which has a gate connected to another end of the current path of the selection transistor, a source and drain that are connected to a dummy plate line, and a paraelectric film serving as a gate insulation film.

A ferroelectric memory device for reading out a high level or low level corresponding to the direction of polarization of a ferroelectric film from a memory cell to a bit line, applying a reference potential from a dummy cell to a reference bit line which makes a complimentary pair with the bit line and comparing the potential of the bit line with the reference bit line which makes a complementary pair with the bit line and comparing the potential of the bit line with the reference potential of the reference bit line to sense and rewrite stored data, comprising:

• a plate line connected to the memory cell;
• a plate driving circuit for pulse-driving a plate line associated with a memory cell selected at the time of data readout;
• and
• a dummy plate line connected to the dummy cell;
• and
• a dummy plate line driving circuit for pulse-driving a dummy plate line associated with a dummy cell connected to a reference bit line which makes a complementary pair with a bit line connected to the selected memory cell,
• wherein said dummy cell includes:
• a selection transistor which has a current path connected at one end to the reference bit line, and a gate connected to a dummy word line;
• and a linear capacitor made of an MOS transistor which has a gate connected to another end of the current path of the selection transistor, a source and drain that are connected to a dummy plate line, and a paraelectric film serving as a gate insulation film.

A ferroelectric memory device comprising:

• a memory cell for storing a high level or low level corresponding to the direction of polarization of a ferroelectric film;
• a bit line to which data stored in the memory cell is read out;
• a reference bit line which makes a complementary pair with the bit line;
• a dummy cell for applying a reference voltage to the reference bit line, said dummy cell including a selection transistor which has a current path connected at one end to the reference bit line, and a gate connected to a dummy word line;
• and a linear capacitor made of an MOS transistor which has a gate connected to another end of the current path of the selection transistor, a source and drain that are connected to the dummy plate line, and a paraelectric film serving as a gate insulation film;
• a sense and rewrite amplifier for comparing the potential of the bit line with the reference potential of the reference bit line to sense and rewrite stored data;
• a plate line driving circuit for pulse-driving a plate line associated with a memory cell selected at the time of data readout;
• and
• a dummy plate line driving circuit for pulse-driving a dummy plate line associated with a dummy cell connected to a reference bit line which makes a complementary pair with a bit line connected to the selected memory cell.