US 6,191,725 B1Granted

Automatic gain control for digital radar intercept receivers

AssigneeHer Majesty the Queen in right of Canada, as represented by the Minister of National Defence of Her Majesty's Canadian Government

InventorPierre Lavoie

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Abstract

An automatic gain control (AGC) circuit for electromagnetic wave receiving systems, such as radar warning receivers, has a number of N parallel paths to which analog IF input signals are applied with each path being connected to one of N inputs of an output switch. Each path contains a free running sampling analog-to-digital converter (ADC) that digitizes an amplified analog IF input, the digitized signals being applied to inputs of digital delay units whose output are supplied to the output switch's inputs. The amplification in each of the N paths is fixed and staggered to provide different fixed amplifications of the IF input to the ADCs. The AGC has a leading edge trigger (LET), a trailing edge trigger (TET) and a track-and-hold circuit that samples and holds the amplitude of an input pulse starting at the leading edge as demarked by the LET. Writing of the digitized signal from the ADCs into digital delay units is started and stopped by signals from a control circuit based on a pulse's LET and TET. A pulse's TET activates the control circuit which compares the sampled and held amplitude in the track-and-hold circuit to references levels and selects a gain setting amongst the N paths that produced the largest digitized version of the analog IF pulse without ADC over-range. The control circuit then sets the output switch to the selected path and reads the data in that path out to provide a pulse-to-pulse AGC signal.

Claims20

Dependent claims

An automatic gain control (AGC) circuit for an electromagnetic wave receiving system, the AGC circuit comprising an analog IF input connected to inputs of N parallel paths wherein an output of each path is connected to one of N inputs of an output switch;

each of the N parallel paths containing a free-running sampling analog-to-digital converter (ADC), an output of each ADC being applied to a digital delay unit having an output forming the output for that path which is connected to one of the N inputs of said output switch, a number of the paths containing a signal amplitude modifier connected to an input of an associated ADC, the signal amplitude modifiers having fixed modification values that are staggered to provide an analog IF input signal to the sampling ADCs where the input to each sampling ADC has a different signal amplitude value;
the AGC circuit having a video detector connected to receive the IF input and to provide a video input signal to a track-and-hold circuit, a means to determine the leading edge of each input signal pulse with a leading edge trigger (LET), a means to determine the trailing edge of each input signal pulse by a trailing edge trigger (TET), wherein the LET is connected to the track-and-hold circuit and to control circuitry with the TET being connected to the control circuitry which has a read/write control line connected to each digital delay unit and a gain control line connected to the output switch, the track-and-hold circuit being connected to the control circuitry and samples and holds the amplitude of an input pulse starting at the leading edge as demarked by the LET while IF signals in each input path with staggered amplitude values are digitized by the free-running ADCs and written into an associated digital delay unit, the writing into the delay units being started and stopped by signals from the control circuitry based on a pulse's LET and TET, the control circuitry comparing the sampled-and-held amplitude from the track-and-hold circuit to reference levels once the TET is activated and then selects a path amongst the N paths that produced the largest digitized version of the analog IF pulse without ADC over-range, the control circuitry then setting the switch to a setting that allows the data from the selected path to be read out to provide a leveled digital IF output at an output of the AGC circuit.

An automatic gain control (AGC) circuit for an electromagnetic wave receiving system, the AGC circuit comprising a video detector connected to receive an IF input signal from the receiving system, a first circuit means connected to an output of the video detector to sample-and-hold the amplitude of an IF input signal pulse, a second circuit means for detecting the leading edge of an input signal pulse to provide a leading edge trigger (LET) signal and a third circuit means for detecting the trailing edge of an input signal pulse to provide a trailing edge trigger (TET) signal which are connected to receive an IF input pulse, an output from the second circuit means (LET) being connected to an input of the first circuit means and to an input of control circuitry, the first circuit means output being connected to the control circuitry, an output from the third circuit mean (TET) being connected to another input of the control circuitry which has a gain control signal line connected to a control input of a switch having N inputs, each of which are connected to outputs of N parallel paths whose inputs are connected to receive an analog IF input signal from the receiving system, each of the N parallel paths having an amplifier connected to receive the analog IF input signal with an output being connected to a free-running sampling analog-to-digital (ADC) converter that provides a digitized IF signal to a digital delay unit having a read/write control line connected to an output from the control circuitry, an output of each digital delay unit being connected to one of N inputs of said switch which has one single output, each of the amplifiers having a different fixed amplification value to provide an IF signal in the paths with staggered amplifications, wherein the writing into the delay units is started and stopped by signals from the control circuitry based on a pulse's LET and TET, the control circuitry comparing the sampled-and-held amplitude from the first circuit means to reference levels once the TET is activated and then selects an amplification gain setting amongst the N paths that produced the largest digitized version of the analog signal IF pulse without ADC over-range, the control circuitry setting the switch to a position that allows the data from the selected path to be read out to provide a leveled digital IF output at the switch's output.

Dependencies are inferred from the claim text.