Digital to analog converter with reduced ringing

In combination for converting binary indications of a value to an analog representation of the value,

• first means for providing binary indications of the value,
• second means responsive to the binary indications of the value for decoding and latching such binary indications without any ringing at any time in the time period during the binary indications,
• third means responsive to the latched indications from the second means for producing currents representative of such latched indications without any ringing at the transitions between such latched indications, and
• fourth means for combining the currents from the third means to provide the analog representations.

In combination for converting binary indications of a value to an analog representation of the value,

• means for providing binary indications of the value,
• a plurality of decoding means each including a first terminal and a second terminal and each responsive to an individual one of the binary indications and to the inverse of such individual one of the binary indications for producing on the first terminal a voltage representative of the individual one of the binary indications and for producing an inverse of such voltage on the second terminal,
• means for providing a clock signal, and
• a plurality of latching means each responsive to the clock signal and to the voltage on the first terminal for the individual one of the binary indications and the inverse voltage on the second terminal for the individual one of the binary indications for latching such voltage and the inverse of such voltage.

In combination for converting binary indications of a value to an analog representation of the value,

• first means for providing binary indications of the value,
• second means for providing a clock signal,
• a plurality of circuits each providing decoding and latching and each responsive to an individual one of the binary indications and to the clock signal for decoding the individual one of the binary indications in synchronism with the clock signal and for latching such decoding to provide a first latched output representing such individual one of the binary indications and to provide a second latched output representing the inverse of such individual one of the binary indications, the first and second latched outputs inhibiting any ringing in the period of such individual one of the binary indications,
• an output impedance, and
• a plurality of current sources each responsive to the first and second latched outputs from an individual one of the decoding and latching circuits and each constructed to pass a current through the output impedance, without any ringing at the transition at the individual one of the binary indications, in accordance with the relative characteristics of the first and second latched outputs.

In combination in a current source for converting a binary representation of a value to an analog representation of the value,

• first means for providing the binary representation,
• second means for providing the inverse of the binary representation,
• a differential amplifier formed from a plurality of MOS transistors of the p type and having a pair of branches,
• third means for introducing the binary representations from the first and second means to the first branch in a first relationship to provide at first particular times an output current dependent upon the binary representation from the first means and the inverse of the binary representation from the second means, and
• fourth means for introducing the binary representations from the first and second means to the second branch in a second relationship inverse to the first relationship to provide an output current at the times other than the first particular times.

In combination for converting binary indications of a value into an analog representation of the value,

• first means for providing the binary indications of the value, each of the binary indications occurring in a finite time interval and having transitions at the beginning and end of the finite time interval,
• second means for providing a plurality of first outputs each representative of an individual one of the binary indications of the value,
• third means for providing a plurality of second outputs each inverse to an individual one of the first outputs,
• an output impedance, and
• a plurality of current sources each responsive to the first and second outputs from an individual one of the binary indications of the value and each constructed to pass a current through the output impedance, without any ringing at the transitions at the individual one of the binary indications, in accordance with the characteristics of the first and second outputs from such individual one of the binary indications.

A digital to analog converter (DAC) comprising:

• an output circuit across which an output signal appears;
• a bias sourer;
• a clock pulse source;
• a plurality of stages arranged in a matrix of cells;
• a selector circuit for turning the cells on and off depending on the state of a multi-bit binary signal;
• each stage comprising a clock actuated switch and a cell selecting switch connected in series between the bias source and the output circuit such that the bias source is applied to the output circuit if the corresponding cell is turned on when a clock pulse appears and is not applied to the output circuit if the corresponding cell is turned off when a clock pulse appears and such that the amplitude of the output signal depends on the cells that are turned on;
• means for connecting the clock pulse source to the clock actuated switch of each stage to render the clock actuated switch of the stage conditionally conductive when a clock pulse appears;
• means for connecting the selector circuit to the cell selecting switch of each stage to render the cell selecting switch of the stage conditionally conductive if the cell is turned on by the state of the binary signal.

A differential digital to analog converter (DAC) comprising;

• an uninverted output circuit across which an uninverted output signal appears;
• an inverted output circuit across which an inverted output signal appears;
• a bias source;
• a clock pulse source;
• a plurality of uninverted and inverted stages arranged in a matrix of cells;
• a selector circuit for turning the cells on and off depending on the state of a multi-bit binary signal;
• each uninverted stage comprising a clock actuated switch and a cell selecting switch connected in series between the bias source and the uninverted output circuit such that the bias source is applied to the uninverted output circuit if the corresponding cell is turned on when a clock pulse appears and is not applied to the uninverted output circuit if the corresponding cell is turned off when a clock pulse appears and such that the amplitude of the uninverted output signal depends on the cells that are turned on;
• each inverted stage comprising a clock actuated switch and a cell selecting switch connected in series between the bias source and the inverted output circuit such that the bias source is applied to the inverted output circuit if the corresponding cell is turned off when a clock pulse appears and is not applied to the inverted output circuit if the corresponding cell is turned on when a clock pulse appears and such that the amplitude of the inverted output signal depends on the cells that are turned off;
• means for connecting the clock pulse source to the clock actuated switch of each stage to render the clock actuated switch of the stage conditionally conductive when a clock pulse appears;
• means for connecting the selector circuit to the cell selecting switch of each uninverted stage to render the cell selecting switch of the stage conditionally conductive if the cell is turned on by the state of the binary signal;
• and
• means for connecting the selector circuit to the cell selecting switch of each inverted stage to render the cell selecting switch of the stage conditionally conductive if the cell is turned off by the state of the binary signal.