Data sampling method and device
AssigneeNEC Corporation
InventorMariko Matsumoto
Life of this patent
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Abstract
Digital data is generated by sampling an analog input signal at a sampling frequency that is N times an A/D sampling frequency that is necessary in an A/D converter. N decimated data strings are generated by decimating the digital data at a ratio of 1/N. Based on the N decimated data strings, a processor produces a digital output signal.
Claims16
A data sampling method for an A/D (analog-to-digital) conversion from an analog input signal to a digital output signal, comprising the steps of:
- a) converting the analog input signal to digital data by sampling the analog input signal at a sampling frequency fs that is N times an A/D sampling frequency that is necessary for the A/D conversion, where N is an integer;
- b) decimating the digital data at a ratio of 1/N to produce N decimated data strings;
- and
- c) selecting the digital output signal from among the N decimated data strings.
A data sampling method for an A/D (analog-to-digital) conversion from an analog input signal to a digital output signal, wherein the analog input signal has been modulated according a predetermined quadrature modulation scheme, comprising the steps of:
- a) converting the analog input signal to digital data by sampling the analog input signal at a sampling frequency fs that is N times an A/D sampling frequency that is necessary for the A/D conversion, where N is an integer and is determined depending on a frequency of the analog input signal;
- b) generating N clock signals which have 1/N the sampling frequency fs and are delayed in order by 1/fs;
- c) decimating the digital data using two clock signals selected from the N clock signals to produce two decimated data strings, wherein a frequency of each of the N decimated data strings is set to a baseband frequency and one of the two clock signals is delayed from the other by π/2;
- and
- d) combining the two decimated data strings to produce the digital output signal as a quadrature-demodulated signal.
A data sampling device for an A/D (analog-to-digital) conversion from an analog input signal to a digital output signal, comprising:
- an oscillator for generating a sampling frequency fs that is N times an A/D sampling frequency that is necessary for the A/D conversion, where N is an integer;
- a converter for converting the analog input signal to digital data by sampling the analog input signal at the sampling frequency fs;
- a decimator for decimating the digital data at a ratio of 1/N to produce N decimated data strings;
- and
- a combiner for selecting the digital output signal from among the N decimated data strings.
A data sampling device for an A/D (analog-to-digital) conversion from an analog input signal to a digital output signal, wherein the analog input signal has been modulated according a predetermined quadrature modulation scheme, comprising the steps of:
- an oscillator for generating a sampling frequency fs that is N times an A/D sampling frequency that is necessary for the A/D conversion, where N is an integer and is determined depending on a frequency of the analog input signal;
- a converter for converting the analog input signal to digital data by sampling the analog input signal at the sampling frequency fs;
- a clock generator for generating N clock signals which have 1/N the sampling frequency fs and are delayed in order by 1/fs;
- a demodulator for demodulating the digital data using two clock signals selected from the N clock signals to produce two decimated data strings, wherein a frequency of each of the N decimated data strings is set to a baseband frequency and one of the two clock signals is delayed from the other by π/2;
- and
- a combiner for combining the two decimated data strings to produce the digital output signal as a quadrature-demodulated signal.
Dependencies are inferred from the claim text.