High-speed digital circuit employing a band-zero-determination-aside (BØDA) architecture

A method for processing a digital signal having first and second time sequential values, each value lying in an unknown one of at least three bands, one above zero, one below zero, and one of zero, comprising:

• processing at least a portion of a first time sequential value of said signal in a first path to determine a first output value of said first time sequential value of said signal;
• concurrently processing at least a portion of said first time sequential value of said signal in a second path to produce a signal indicating if said first time sequential value of said signal corresponding to band zero;
• processing at least a portion of a second time sequential value of said signal in a third path to determine a second output value of said second time sequential value of said signal;
• concurrently processing at least a portion of a second time sequential value of said signal in a fourth path to produce a signal indicating if said second time sequential value signal is of band zero;
• adding said first and second output values of said signals;
• multiplexing said first output value, said second output value and said added first and second output values according to said signals indicating if said first and second time sequential value signals belong to band zero to produce an output signal of value of zero if said signals are both determined to belong to band zero, to be said first output value if said signal indicating if said second time sequential value signal belongs to band zero indicates said second time sequential value signal belongs to band zero, to be said second output value if said signal indicating if said first time sequential value signal belongs to band zero indicates said first time sequential value signal belongs to band zero, and said added said first and second output values if neither said signals indicating if said first and second time sequential values signal belongs to band zero indicates an addition of the modified errors.

A system for processing a digital signal having an unknown value in one of at least three bands, one above a band zero, one below the band zero, and one of band zero, comprising:

• a first circuit in a first path to receive at least a portion of said signal to determine a function of said signal;
• a second circuit in a second path to receive at least a portion of said signal to determine if said signal belongs to the band zero concurrently with an operation of said first circuit to produce an output signal that corresponds to band 0;
• and
• an output circuit to produce an output signal of value of zero if said signal is determined to belong to band zero, otherwise to produce an output signal having a value of said signal.

A system for processing a digital signal having first and second time sequential values, each value lying in an unknown one of at least three bands, one above zero, one below zero, and one of zero, comprising:

• a first circuit for processing at least a portion of a first time sequential value of said signal in a first path to determine a first output value of said first time sequential value of said signal;
• a second circuit for concurrently processing at least a portion of said first time sequential value of said signal in a second path to produce a signal indicating if said first time sequential value of said signal has a value of zero;
• a third circuit for processing at least a portion of a second time sequential value of said signal in a third path to determine a second output value of said second time sequential value of said signal;
• a fourth circuit for concurrently processing at least a portion of a second time sequential value of said signal in a fourth path to produce a signal indicating if said second time sequential value signal has a value of zero;
• an adder for adding said first and second cutout values of said signals;
• and
• a multiplexer for multiplexing said first output value, said second output value and said added first and second cutout values according to said signals indicating if said first and second time sequential value signals have a value of zero to produce an output signal of value of zero if said signals are both determined to belong lo band zero, to be said first output value if said signal indicating if said second time sequential value signal has a value of zero indicates said second time sequential value signal has a value of zero, to be said second output value if said signal indicating if said first time sequential value signal has a value of zero indicates said first time sequential value signal has a value of zero, and said added said first and second output values if neither said signals indicating if said first and second time sequential values signal has a value of zero indicates said first and second time sequential value signals has a value of zero.

A system for processing a digital signal having an initial bit rate, comprising:

• separate paths A and B for processing the digital signal;
• and
• a circuit for facilitating referenced processing between said separate paths;
• wherein the processing on path A is accomplished with concurrent processing on path B, thereby enabling processing on path B at approximately the initial bit rate of the digital signal.

A system for processing a digital signal having a bit rate, comprising:

• separate paths A and B for processing the digital signal;
• and
• a structure facilitating referenced processing between said separate paths,
• wherein the processing on path A may be accomplished at a different time than that on path B, thus enabling processing on path B near the bit rate of the digital signal.