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US 6,191,713 B1Granted
Conversion between serial bus cycles and parallel port commands using a state machine
AssigneeIntel Corporation
InventorsDavid G. Ellis, Gene A. Frederiksen
Life of this patent
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Abstract
The present invention is directed to a method and apparatus for converting between serial bus cycles and parallel port commands. A serial bus processor processes a serial bus transaction which is represented by the serial bus cycles and is responsive to the parallel port commands. A state machine circuit is coupled to the serial bus processor to provide a plurality of states corresponding to the serial bus transaction. The state machine circuit transitions from one of the states to any one of the states in response to a change condition asserted by a state signal.
Claims37
A method comprising:
- processing a serial bus transaction, the processing comprising:
- synchronizing a non return to zero invert (NRZI) encoded packet of data,
- decoding the NRZI encoded packet of data,
- removing redundant stuffed bits in the decoded stream of data, and
- converting the decoded stream of data into parallel data;
- and
- configuring a state machine corresponding to the serial bus transaction, the serial bus transaction being represented by serial bus cycles and responsive to parallel port commands, the state machine including a plurality of states;
- receiving a state signal, the state signal asserting a change condition;
- and
- transitioning from one of the states to any one of the states in response to the change condition to complete the serial bus transaction.
7 more elements
An apparatus comprising:
- a receiver processor to process a serial bus transaction, the serial bus transaction being represented by serial bus cycles and responsive to parallel port commands, the receiver processor comprising:
- a synchronizer to synchronize a non return to zero invert (NRZI) encoded packet of data sent by a serial bus device,
- an NRZI decoder coupled to the synchronizer to decode the NRZI encoded packet of data,
- an unpacking circuit coupled to the NRZI decoder to remove redundant stuffed bits in the decoded stream of data, and
- a de-serializer coupled to the unpacking circuit to convert the unpacked packet of data into parallel data;
- and
- a state machine circuit coupled to the receiver processor to provide a plurality of states corresponding to the serial bus transaction, the state machine circuit transitioning from one of the states to any one of the states in response to a change condition asserted by a state signal.
4 more elements
An apparatus comprising:
- a transmitter processor to process a serial bus transaction, the serial bus transaction being represented by the serial bus cycles and responsive to the parallel port commands, the transmitter processor comprising:
- a multiplexer to select a data for transmission,
- a cyclic redundant code (CRC) generator coupled to the multiplexer to generate a CRC corresponding to the selected data,
- a packing circuit coupled to the multiplexer to insert redundant stuffed bits in the selected data, and
- a non return to zero invert (NRZI) encoder coupled to the packing circuit to encode the selected data;
- and
- a state machine circuit coupled to the transmitter processor to provide a plurality of states corresponding to the serial bus transaction, the state machine circuit transitioning from one of the states to any one of the states in response to a change condition asserted by a state signal.
4 more elements
A system comprising:
- a serial bus device;
- a host processor;
- a parallel port device coupled to the host processor to provide a communication interface between the host processor and the serial bus device, the parallel port device receiving parallel port commands from the host processor;
- and
- a serial bus-to-parallel port interface (UPI) circuit coupled to the parallel port device and the serial bus device to convert between serial bus cycles and the parallel port commands, the UPI circuit comprising:
- a receiver processor to process a serial bus transaction, the serial bus transaction being represented by serial bus cycles and responsive to the parallel port commands, the receiver processor comprising:
- a synchronizer to synchronize a non return to zero invert (NRZI) encoded packet of data sent by a serial bus device,
- an NRZI decoder coupled to the synchronizer to decode the NRZI encoded packet of data,
- an unpacking circuit coupled to the NRZI decoder to remove redundant stuffed bits in the decoded stream of data, and
- a de-serializer coupled to the unpacking circuit to convert the unpacked packet of data into parallel data;
- and
- a state machine circuit coupled to the receiver processor to provide a plurality of states corresponding to the serial bus transaction, the state machine circuit transitioning from one of the states to any one of the states in response to a change condition asserted by a state signal.
9 more elements
A system comprising:
- a serial bus device;
- a host processor;
- a parallel port device coupled to the host processor to provide a communication interface between the host processor and the serial bus device, the parallel port device receiving parallel port commands from the host processor;
- and
- a serial bus-to-parallel port interface (UPI) circuit coupled to the parallel port device and the serial bus device to convert between serial bus cycles and the parallel port commands, the UPI circuit comprising:
- a transmitter processor to process a serial bus transaction, the serial bus transaction being represented by serial bus cycles and responsive to the parallel port commands, the transmitter processor comprising:
- a multiplexer to select a data for transmission,
- a cyclic redundant code (CRC) generator coupled to the multiplexer to generate a CRC corresponding to the selected data,
- a packing circuit coupled to the multiplexer to insert redundant stuffed bits in the selected data, and
- a non return to zero invert (NRZI) encoder coupled to the packing circuit to encode the selected data;
- and
- a state machine circuit coupled to the transmitter processor to provide a plurality of states corresponding to the serial bus transaction, the state machine circuit transitioning from one of the states to any one of the states in response to a change condition asserted by a state signal.
9 more elements
A method comprising:
- processing a serial bus transaction, the processing comprising:
- selecting a data for transmission,
- generating a cyclic redundant code (CRC) corresponding to the selected data,
- inserting redundant stuffed bits in the selected data, and
- encoding the selected data;
- configuring a state machine corresponding to the serial bus transaction, the serial bus transaction being represented by serial bus cycles and responsive to parallel port commands, the state machine including a plurality of states;
- receiving a state signal, the state signal asserting a change condition;
- and
- transitioning from one of the states to any one of the states in response to the change condition to complete the serial bus transaction.
6 more elements
Dependencies are inferred from the claim text.