System and method for comparing values during logic analysis

A field programmable gate array configured for comparing logical values, comprising:

• means for receiving an N-bit sampled value, where N defines the number of bits in the N-bit sampled value;
• means for matching an M-bit portion of the N-bit sampled value with one of a number of M-bit portion variations, wherein a matching output is generated depending upon the M-bit portion variation that matches the M-bit portion;
• and
• means for performing an AND operation on all of the matching outputs.

A system for comparing logical values, comprising:

• a system to generate a configuration string that is applied to a field programmable gate array, the field programmable gate array comprising:
• a number of inputs;
• a number of lookup tables, each of the lookup tables being configurable to receive data from the inputs, each of the lookup tables generating a lookup table output therefrom;
• an AND gate having a number of inputs that are configurable to receive the lookup table outputs;
• and
• wherein the configuration string configures the field programmable gate array to receive an N-bit sampled value at the number of inputs, where N defines the number of bits in the N-bit sampled value, and, the configuration string configures each of the lookup tables to receive an M-bit portion of the N-bit sampled value, the lookup tables generating a lookup table output in response to the M-bit portion that is applied to the inputs of the AND gate.

A system for comparing logical values, comprising:

• means for generating a configuration string that is applied to a field programmable gate array, the field programmable gate array comprising:
• a number of inputs;
• a number of lookup tables, each of the lookup tables being configurable to receive data from the inputs, and each the lookup tables generating a lookup table output therefrom;
• an AND gate having a number of inputs that are configurable to receive the lookup table outputs;
• and
• wherein the configuration string configures the field programmable gate array to receive an N-bit sampled value at the number of inputs, where N defines the number of bits in the N-bit sampled value, and, the configuration string configures each of the lookup tables to receive an M-bit portion of the N-bit sampled value, the lookup tables generating a lookup table output in response to the M-bit portion that is applied to the inputs of the AND gate.

A method for comparing logical values in a field programmable gate array, comprising the steps of:

• receiving an N-bit sampled value, where N defines the number of bits in the N-bit sampled value;
• matching a number of M-bit portions of the N-bit sampled value with one of a number of M-bit portion variations, wherein a matching output is generated depending upon the M-bit portion variation that matches the M-bit portion;
• and
• performing an AND operation on all of the matching outputs.