Frequency synthesizer with a phase-locked loop with multiple fractional division

A frequency synthesizer with a phase-locked loop with multiple fractional division, of the type comprising a single phase-locked loop controlled by a reference clock and formed by a voltage-controlled oscillator, a programmable divider with variable division rank M, a phase detector, and a loop filter, comprising in addition a predetermined number n of fractional division structures, each implementing a desired frequency step lower than the reference frequency Fref, and wherein each fractional division structure is coupled in parallel with said programmable divider in order to add fractional increments Pi to said division rank M such that the ratio between the frequency Fvco provided by said voltage-controlled oscillator and said reference frequency Fref be defined as a function of said increments Pi by the relationship:

• F vco = ( M + ∑ 1 n ⁢ P i ) ⁢ F ref .