Zero power fuse circuit using subthreshold conduction
AssigneeClear Logic, Inc.
InventorWilliam L. Devanney
Life of this patent
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Abstract
A zero static power laser fuse circuit is formed from one laser fuse and three transistors, with the fuse connected in series to a reverse-biased diode and with the common node of the fuse and diode connected to the input of a driving circuit, such as a CMOS inverter. Blowing the fuse allows a small subthreshold conduction current to flow to the common node and pull the node to the opposite logic state. This fuse circuit, which allows the capacitance at the common node to be minimized for zero static power operation, requires less circuit area than previous zero static power fuse circuits.
Claims26
A configurable fuse circuit, comprising:
- a reverse-biased MOS transistor having a gate, a source, and a drain, wherein said source and said gate are coupled together to a first potential;
- a fuse having first and second terminals, wherein said first terminal is coupled to said drain of said MOS transistor at a node X, wherein the only source or drain coupled to said node X is the drain of said MOS transistor, and said second terminal is coupled to a second potential;
- and
- a driving circuit having an input node and an output node Y, wherein said input node is coupled to said node X.
A configurable fuse circuit, comprising:
- a first MOS transistor, wherein the source and the gate of said first MOS transistor are coupled together to a first potential;
- a fuse having first and second terminals, wherein said first terminal is coupled to the drain of said first MOS transistor at a node X, wherein the only source or drain coupled to said node X is the drain of said first MOS transistor, and said second terminal is coupled to a second potential;
- a second MOS transistor, wherein the gate and the source of said second MOS transistor is coupled to said node X and to a third potential, respectively;
- and
- a third MOS transistor, wherein the gate and the source of said third MOS transistor is coupled to said node X and to a fourth potential, respectively, and wherein the drains of said second and third MOS transistors are coupled together at an output node Y.
Dependencies are inferred from the claim text.