US 6,191,637 B1 · Switched capacitor bias circuit for generating a reference signal proportional to absolute temperature, capacitance and clock frequency

Abstract

An integrated switched capacitor bias circuit for generating a reference signal which is proportional to absolute temperature, a capacitance and a clock signal frequency. A current mirror circuit generates a primary current and a mirrored current. Under the control of a clock signal, a switched capacitor circuit uses the mirrored current to constantly accumulate charges on primary capacitor while also alternately sharing such charges with and then discharging one of two additional capacitors. The magnitude of the current drawn by the switched capacitor circuit is a factor of the junction area of a diode and absolute temperature. To maintain equality of the primary and mirrored currents, a node voltage within the current mirror circuit is monitored by a bias circuit which provides a bias signal for controlling the current mirror circuit. An additional current replication stage is driven by the current mirror circuit to provide an additional mirrored current which is proportional to a product of absolute temperature and the frequency of the clock signal.

Claims26

Dependent claims

An apparatus including an integrated switched capacitor bias circuit for generating a reference signal which is proportional to absolute temperature, a capacitance and a clock signal frequency, said integrated switched capacitor bias circuit comprising:

a current mirror circuit that includes primary, first and second circuit branches and, in response to a bias voltage received via said primary and first circuit branches, provides a node voltage via said first circuit branch and provides a primary current, a first mirrored current and a second mirrored current via said primary, first and second circuit branches, respectively, wherein said node voltage is responsive to said first mirrored current;
a bias circuit, coupled to said current mirror circuit, that provides said bias voltage in response to said node voltage;
and
a switched capacitor circuit, coupled to said first current mirror circuit branch, that includes a capacitance and, in response to first and second clock signals which are equal in frequency and mutually inverse in phase, receives and conducts said first mirrored current in proportion to an absolute temperature of said switched capacitor circuit, said capacitance and said clock signal frequency;
wherein said second mirrored current is proportional to a product of said absolute temperature, said capacitance and said clock signal frequency.

2 more elements

a current mirror circuit that provides a primary current, first and second mirrored currents and a node voltage in response to a bias voltage, wherein said node voltage is responsive to said first mirrored current;
a bias circuit, coupled to said current mirror circuit, that provides said bias voltage in response to said node voltage;
and
a switched capacitor circuit, coupled to said current mirror circuit, that includes a capacitance and, in response to first and second clock signals which are equal in frequency and mutually inverse in phase, receives and conducts said first mirrored current in proportion to an absolute temperature of said switched capacitor circuit, said capacitance and said clock signal frequency;
wherein said second mirrored current is proportional to a product of said absolute temperature, said capacitance and said clock signal frequency;
and
wherein said switched capacitor circuit comprises:
a primary capacitive circuit that accumulates a primary electrical charge in response to said first mirrored current;
a first switched capacitive circuit, coupled to said primary capacitive circuit, that, in response to said first and second clock signals, alternately
accumulates a first shared electrical charge from said first capacitive circuit and a first switched electrical charge, and
discharges said accumulated first shared and switched electrical charges;
and
a second switched capacitive circuit, coupled to said primary capacitive circuit, that, in response to said first and second clock signals, alternately
accumulates a second shared electrical charge from said first capacitive circuit and a second switched electrical charge, and
discharges said accumulated second shared and switched electrical charges.

12 more elements

A method of generating a reference signal which is proportional to absolute temperature, a capacitance and a clock signal frequency, comprising the steps of:

receiving a bias voltage via primary and first circuit branches and in response thereto generating a node voltage via said primary circuit branch, a primary current via said primary circuit branch, a first mirrored current via said first circuit branch, and a second mirrored current via said first circuit branch, wherein said node voltage is responsive to said first mirrored current;
receiving said node voltage and in response thereto generating said bias voltage;
and
receiving, with a capacitive circuit having a capacitance, first and second clock signals which are equal in frequency and mutually inverse in phase and in response thereto receiving and conducting said first mirrored current in proportion to an absolute temperature, said capacitance and said clock signal frequency;
wherein said second mirrored current is proportional to a product of said absolute temperature, said capacitance and said clock signal frequency.

2 more elements

A method of generating a reference signal which is proportional to absolute temperature, a capacitance and a clock signal frequency, comprising the steps of:

receiving a bias voltage and in response thereto generating a primary current, first and second mirrored currents and a node voltage, wherein said node voltage is responsive to said first mirrored current;
receiving said node voltage and in response thereto generating said bias voltage;
and
receiving, with a capacitive circuit having a capacitance, first and second clock signals which are equal in frequency and mutually inverse in phase and in response thereto receiving and conducting said first mirrored current in proportion to an absolute temperature, said capacitance and said clock signal frequency;
wherein said second mirrored current is proportional to a product of said absolute temperature, said capacitance and said clock signal frequency and
wherein said step of receiving, with a capacitive circuit having a capacitance, first and second clock signals which are equal in frequency and mutually inverse in phase and in response thereto receiving and conducting said first mirrored current in proportion to an absolute temperature, said capacitance and said clock signal frequency comprises:
receiving said first mirrored current and in response thereto accumulating a primary electrical charge;
receiving said first and second clock signals and in response thereto alternately
accumulating
a first shared electrical charge from said primary electrical charge and
a first switched electrical charge, and
discharging said accumulated first shared and switched electrical charges;
and
receiving said first and second clock signals and in response thereto alternately
accumulating
a second shared electrical charge from said primary electrical charge and
a second switched electrical charge, and
discharging said accumulated second shared and switched electrical charges.

15 more elements

Dependencies are inferred from the claim text.

Switched capacitor bias circuit for generating a reference signal proportional to absolute temperature, capacitance and clock frequency

Life of this patent

Switched capacitor bias circuit for generating a reference signal proportional to absolute temperature, capacitance and clock frequency

Life of this patent

Abstract

Claims26