Input buffer/level shifter
AssigneeCypress Semiconductor Corporation
InventorsDaniel Eric Cress, Jeffery Scott Hunt, Muthu Nagarajan
Life of this patent
Estimating the term…
Abstract
A circuit is presented comprising a first device and a second device. The first device may be configured to operate at a first supply voltage and may be configured to generate a pull-up signal in response to an input signal. The second device may be configured to operate at a second supply voltage. The second supply voltage may be lower than the first supply voltage. The second device may be configured to generate an output in response to (i) the input signal and (ii) the pull-up signal.
Claims18
A circuit comprising:
- a first device configured to operate at a first supply voltage and generate a pull-up signal in response to an input signal;
- and
- a CMOS inverter and an NMOS pull-up transistor configured to operate at a second supply voltage and generate an output signal in response to (i) said input signal and (ii) said pull-up signal.
A circuit comprising:
- means for generating a pull-up signal in response to an input signal, said pull-up generating means operating at a first supply voltage;
- and
- means for generating an output signal in response to (i) said input signal and (ii) said pull-up signal, said output generating means (i) comprises a CMOS inverter and an NMOS pull-up transistor, and (ii) operates at a second supply voltage.
A method for buffering and/or level shifting an input signal comprising the steps of:
- (A) generating a pull-up signal in response to an input signal, wherein said input signal and said pull-up signal swing between a ground voltage and a first supply voltage;
- and
- (B) generating an output signal in response to (i) said input signal and (ii) said pull-up signal, wherein said output signal swings between said ground voltage and a second supply voltage, wherein step (B) comprises the sub-steps of (B-1) testing the state of said input signal;
- (B-2) if said input signal is at a first logic state, (i) turning off an NMOS pull-down device and (ii) turning on an NMOS pull-up device;
- and (B-3) if said input signal is at a second logic state, (i) turning on said NMOS pull-down device and (ii) turning off said NMOS pull-up device.
Dependencies are inferred from the claim text.