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US 6,191,633 B1Granted
Semiconductor integrated circuit with protection circuit against electrostatic discharge
AssigneeNEC Corporation
InventorsTakeo Fujii, Kaoru Narita, Yoko Horiguchi
Life of this patent
Estimating the term…
Abstract
A Semiconductor integrated circuit with a protection circuit against electrostatic discharge. A clamping element is connected with MIS transistor to prevent the breakdown under the charged device model. A parasitic bipolar transistor, a MOS transistor or MIS transistor whose gate is composed of an insulating film thicker than that of the transfer gate, can be used as the clamping element.
Claims16
A semiconductor integrated circuit which comprises:
- an input pad;
- an internal circuit;
- a transfer gate connected between said input pad and said internal circuit;
- and
- a clamping element which is connected with a gate of said transfer gate for protecting said transfer gate.
2 more elements
A semiconductor integrated circuit which comprises:
- an input pad;
- a MIS transistor whose gate is connected with power supply or ground voltage, wherein either source or drain of said MIS transistor is coupled with said input pad;
- and
- a clamping element which is connected between said gate and either of said source or said drain.
1 more element
A semiconductor integrated circuit which comprises:
- an input pad;
- a FET transistor whose gate is coupled with said input pad, wherein either of the source or the drain of said FET transistor is coupled with power supply or ground voltage;
- and
- a clamping element connected between said gate and either of said source or said drain, which clamping element includes a parasitic bipolar transistor adjacent to said FET transistor.
1 more element
A semiconductor integrated circuit which comprises:
- an input pad;
- a FET transistor whose gate is coupled with said input pad, wherein either of the source or the drain of said MIS transistor is coupled with power supply or ground voltage;
- and
- a clamping element connected between said gate and either of said source or said drain, which includes another FET transistor whose gate comprises an insulating film thicker than that of said FET transistor.
1 more element
Dependencies are inferred from the claim text.