Clock generation circuit and semiconductor integrated circuit

A semiconductor integrated circuit comprising a clock generation circuit for generating an internal clock according to a clock supplied from the outside, a buffer for storing data supplied from the outside, and a latch circuit for latching the input data output from the buffer in accordance with the internal clock, said clock generation circuit comprising:

• a clock wiring having opposed first and second ends, through which a clock is transmitted from the first end to the second end;
• and
• a plurality of clock phase adjustment circuits for generating internal clocks in accordance with the clock supplied from the clock wiring, each clock phase adjustment circuit comprising:
• a first-end side terminal and a second-end side terminal which are connected to a first-end side point and a second-end side point of the circuit, respectively, said points being positioned on both sides of a reference point of the clock wiring;
• delay means for delaying a clock supplied from one of the terminals and outputting an internal clock;
• and
• delay control means for performing feedback control on a delay of the clock in the delay means in accordance with the phase of the clock supplied from the other terminal so that the phase of the internal clock matches the phase of the clock at the reference point of the clock wiring.