Delay circuit and oscillator circuit using same

A delay circuit for delaying at least one of a timing of a rising edge and a timing of a falling edge of an input signal alternating between first and second levels, comprising:

• a charge pump in which first and second field-effect transistors of different channels are serially connected;
• a capacitor connected in parallel with the first field-effect transistor;
• a charging current control circuit for controlling magnitude of a charging current on the basis of one of the rising edge delay time and falling edge delay time and passing the charging current into said capacitor via the second field-effect transistor of said charge pump when the input signal is at the first level;
• a discharge current control circuit for controlling magnitude of a discharge current on the basis of the other of the rising edge delay time and falling edge delay time and releasing the discharge current form said capacitor via the first field-effect transistor when the input signal is at the second level;
• and
• a discrimination circuit for outputting a signal of a prescribed logic level based upon a terminal voltage of the capacitor.

An oscillator circuit comprising:

• an odd number of delay circuits serially connected into ring form, input and output signal levels of said delay circuits being in inverse relation to each other, each delay circuit comprising:
• a charge pump in which first and second field-effect transistors of different channels are serially connected;
• a capacitor connected in parallel with the first field-effect transistor;
• a charging current control circuit for controlling magnitude of a charging current on the basis of one of the rising edge delay time and falling edge delay time and passing the charging current into said capacitor via the second field-effect transistor of said charge pump when the input signal is at the first level;
• a discharge current control circuit for controlling magnitude of a discharge current on the basis of the other of the rising edge delay time and falling edge delay time and releasing the discharge current from said capacitor via the first field-effect transistor when the input signal is at the second level;
• and
• a discrimination circuit for outputting a signal of a prescribed logic level based upon a terminal voltage of the capacitor.

An oscillator circuit comprising;

• an even number of delay circuits serially connected into ring form, input and output signal levels of said delay circuits not being in inverse relation to each other, each delay circuit comprising:
• a charge pump in which first and second field-effect transistors of different channels are serially connected;
• a capacitor connected in parallel with the first field-effect transistor;
• a charging current control circuit for controlling magnitude of a charging current on the basis of one of the rising edge delay time and falling edge delay time and passing the charging current into said capacitor via the second field-effect transistor of said charge pump when the input signal is at the first level;
• a discharge current control circuit for controlling magnitude of a discharge current on the basis of the other of the rising edge delay time and falling edge delay time and releasing the discharge current from said capacitor via the first field-effect transistor when the input signal is at the second level;
• and
• a discrimination circuit for outputting a signal of a prescribed logic level based upon a terminal voltage of the capacitor.