US 6,191,629 B1Granted

Interlaced master-slave ECL D flip-flop

AssigneeConexant Systems, Inc.

InventorsBiagio Bisanti, Akbar Ali

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Abstract

A D flip-flop circuit operating in master-slave configuration which has low power consumption and is capable of high-speed operation, and a method for lowering power consumption in such a circuit is provided. The circuit embodiment includes two latches, each with a switching and memory section, and two interlaced current sources. In response to the active high clock signal the master latch memory section uses the current from the first current source while the slave latch switching section uses the current from the second current source, and vice versa. The switching section of each latch is biased with a higher current than the memory section, to provide the circuit with low power consumption. The output current provided to the switching section is preferably substantially twice the magnitude of the current provided to the memory section. The ratio of the currents of the current sources for the switching and memory section is preferably in the range of about 30% to 70%, depending on the clock frequency.

Claims10

Dependent claims

A D flip-flop circuit operating in master-slave configuration at high speed with low power consumption, comprising:

a first current source;
a second current source;
a ground level;
a master latch having a switching section and a memory section, a pair of data input terminals and a pair of differential signal output terminals;
a slave latch having a switching section, a memory section, and a pair of differential signal input terminals connected to the differential signal output terminals of the master latch;
a power supply connected to said first and second latch;
said master latch operating with an active high clock signal and transparent while the slave latch is latched, and the slave latch operating with an active low clock signal and transparent while the master latch is latched, said latches clocked in sequence;
said first and second current sources being interlaced, wherein at the active high clock signal the master latch switching section uses the current from the first current source while the slave latch memory section uses the current from the second current source, and at the active low clock signal the master latch memory section uses the current from the second current source while the slave latch switching section uses the current from the first current source;
and
the switching section of each said latch biased with a higher current than the memory section, thereby resulting in the D flip-flop with low power consumption.

7 more elements

Dependencies are inferred from the claim text.