Integrated circuit having adjustable delay units for clock signals
AssigneeSiemens Aktiengesellschaft
InventorPatrick Heyne
Life of this patent
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Abstract
An integrated circuit includes a first adjustable delay unit to which a first clock signal is fed and a second adjustable delay unit to which a second clock signal is fed. A phase detector is connected to the input and to the output of the first delay unit. A control unit serves for correcting a phase difference obtained by the phase detector and controls the delay time of the first delay unit in a corresponding manner. The control unit additionally sets the delay time of the second delay unit to essentially the same value as that of the first delay unit. Furthermore, the output of the second delay unit is connected to the input of a third adjustable delay unit.
Claims7
An integrated circuit, comprising:
- a first delay unit having an adjustable delay time, an input for feeding in a first clock signal and an output;
- a second delay unit having an adjustable delay time, an input for feeding in a second clock signal and an output;
- a phase detector having a first input connected to said input of said first delay unit and a second input connected to said output of said first delay unit;
- a control unit controlling the delay time of said first delay unit for correcting a phase difference ascertained by said phase detector and setting the delay time of said second delay unit to substantially the same value as that of said first delay unit;
- a circuit unit having a first input connected to said output of said first delay unit and a second input connected to said output of the second delay unit;
- and
- a third delay unit having an adjustable delay time, said third delay unit connected between said output of said second delay unit and said second input of said circuit unit.
Dependencies are inferred from the claim text.