Time interleaved common mode feedback circuit with process compensated bias
AssigneeATI International SRL
InventorMinh Watson
Life of this patent
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Abstract
A time-multiplexed common mode feedback circuit provides a common mode feedback signal during active phases of a clock signal. The common mode feed back circuit includes capacitors which are charged during the inactive phases of the clock signals. In one embodiment, the common mode feedback signal is provided by two generator circuits each driven by a respective one of two non-overlapping clock signals. In that embodiment, the generator circuits provide the common mode feedback signal during the active phases of their respective clock signals.
Claims12
A common mode feedback circuit providing a common mode feedback signal at an output terminal based on a differential signal, comprising:
- a first circuit receiving said differential signal and a first clock signal, the first circuit providing, during an active phase of said first clock signal, at said output terminal a voltage substantially equal to a common mode voltage component of said differential signal plus a bias voltage;
- and
- a second circuit receiving said differential signal and a second clock signal, said second clock signal being active during an inactive phase of said first clock signal, said second circuit providing, during an active phase of said second clock signal, at said output terminal a voltage approximating said common mode voltage component of said differential signal plus said bias voltage.
A method for providing a common mode feedback signal based on a differential signal, said method comprising:
- providing as said common mode feedback signal, during an active phase of a first clock signal, a voltage substantially equal to a common mode voltage component of said differential signal plus a bias voltage;
- and
- providing as said common mode feedback signal, during an active phase of a second clock signal, said second clock signal being active during an inactive phase of said first clock signal, a voltage substantially equal to said common mode voltage component of said differential signal plus said bias voltage.
A current source providing an output current, comprising:
- a first transistor having an output terminal and a control terminal, said first transistor having a first channel length, said first transistor receiving a reference voltage at said control terminal and generating a first current at said output terminal, and
- a second transistor having an output terminal and an input terminal, said second transistor having a second channel length longer than said channel length of said first transistor, said second transistor receiving at its control terminal said reference voltage and generating at its output terminal a second current;
- wherein said output terminal of said first transistor and said output terminal of said second transistor are coupled to provide said output current as a sum of said first current and said second current.
A method for providing an output current, comprising:
- coupling a first transistor of a first channel length, such that said first transistor receives a reference voltage at a control terminal and generates a first current at an output terminal;
- coupling a second transistor of a second channel length longer than said channel length of said first transistor, such that said second transistor receives at its control terminal said reference voltage and generates at its output terminal a second current;
- and
- combining said first and second currents to provide said output current.
Dependencies are inferred from the claim text.