Contention-free, low clock load domino circuit topology
AssigneeIntel Corporation
InventorsEric Gayles, Bharat Bhushan, Debashree Ghosh
Life of this patent
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Abstract
A domino logic circuit includes a first domino gate that evaluates one or more inputs responsive to a clock signal, a reset gate, and a second domino gate having a first input coupled to the output of the first domino gate. A first input of a reset gate is coupled to the output of the first domino gate, with a second input of the reset gate being coupled to the output of the second domino gate. The reset gate outputs a precharge signal coupled to a second input of the second domino gate when the second domino gate is discharged and the output of the first domino gate changes state such that a high-to-low transition occurs at the first input of the second domino gate.
Claims20
A domino logic circuit comprising:
- a first domino gate that evaluates one or more inputs, and provides an output, responsive to a clock signal;
- a second domino gate having a first input coupled to the output of the first domino gate, a second input, and an output;
- and
- a reset gate having a first input coupled to the output of the first domino gate, a second input coupled to the output of the second domino gate, and an output that provides a precharge signal coupled to the second input of the second domino gate when the output of the second domino gate is discharged and the output of the first domino gate changes state such that a high-to-low transition occurs at the first input of the second domino gate.
A domino logic circuit comprising:
- a pair of first stage domino gates, each having one or more inputs, and an output that represents a logical function of the one or more inputs, the output evaluating the logical function responsive to a clock signal;
- a second stage domino gate having a first PMOS device coupled between a supply potential and an output, and first and second NMOS devices coupled in parallel between the output of the second stage domino gate and ground, the gates of the first and second NMOS devices each being respectively coupled to one of the outputs of the pair of first stage domino gates;
- and
- a reset gate having first and second inputs respectively coupled to one of the outputs of the pair of first stage domino gates, and an output that provides a precharge signal coupled to the gate of the first PMOS device when the output of the second stage domino gate is discharged and the gates of the first and second NMOS devices are both low.
A domino pipeline comprising:
- a plurality of pipeline stages, each pipeline stage comprising a first domino gate coupled to a series of one or more second domino gates;
- each of the second domino gates having a precharge input, an evaluate input, and an output, the precharge input of each second domino gate being driven by a corresponding NAND gate having a first input coupled to an output of a preceding gate and a second input coupled to the output of the second domino gate such that the precharge input is asserted when the output of the second domino gate is discharged and the output of the preceding gate transitions in a way so as to drive the output of the second domino gate high;
- and
- wherein each of the first domino gates is clocked and each of the second domino gates is not clocked.
Dependencies are inferred from the claim text.