Low power, high speed level shifter
AssigneeMicron Technology, Inc.
InventorsTodd A. Merritt, Troy A. Manning
Life of this patent
Estimating the term…
Abstract
A voltage level translator is disclosed which translates a CMOS input signal into a CMOS output signal where the low voltage level of the output signal is equal to the high voltage level of the input signal. The voltage level translator is described in an integrated circuit such as memory circuits, including DRAMs. Specifically, the voltage level translator produces an output signal which can be used as a gate voltage on a pre-charge transistor for a booted circuit where the gate voltage need only drop to the high voltage level of the input signal to shut the transistor off. The voltage level translator described, therefore, reduces the time and power required to translate an input signal by limiting the voltage swing of the output signal.
Claims9
An integrated circuit memory device comprising:
- a voltage supply connection to receive a first voltage (Vcc);
- a voltage pump circuit to provide a second voltage (Vccp) on a Vccp node, the second voltage is greater than the first voltage;
- and
- a voltage level translator circuit comprising:
- an input node;
- a first N-channel transistor having a source node coupled to a ground voltage node, a drain node, and a gate node coupled to the input node;
- a second N-channel transistor having a source node coupled to the drain node of the first N-channel transistor, a drain node, and a gate node coupled to the voltage supply connection;
- a third N-channel transistor having a source node coupled to the input node, a drain node, and a gate node coupled to the voltage supply connection;
- a fourth N-channel transistor having a source node coupled to the drain node of the third N-channel transistor, a drain node, and a gate node coupled to the Vccp node;
- a first P-channel transistor having a source node coupled to the Vccp node, a drain node coupled to a drain node of the second N-channel transistor, and a gate node coupled to the drain node of the fourth N-channel transistor;
- a second P-channel transistor having a source node coupled to the Vccp node, a drain node coupled to a drain node of the fourth N-channel transistor, and a gate node coupled to the drain node of the second N-channel transistor;
- a third P-channel transistor having a source node coupled to the Vccp node, a drain node coupled to an output node of the voltage level translator circuit, and a gate node coupled to the drain node of the first P-channel transistor;
- a fourth P-channel transistor having a source node coupled to the output node, a drain node, and a gate node coupled to the gate node of the first P-channel transistor;
- and
- a fifth N-channel transistor having a source node coupled to the voltage supply connection, a drain node coupled to the drain node of the fourth P-channel transistor, and a gate node coupled to the Vccp node.
Dependencies are inferred from the claim text.