Logic circuit having reduced power consumption
AssigneeNEC Corporation
InventorHiroshi Koga
Life of this patent
Estimating the term…
Abstract
A logic circuit which is driven at low voltage and operates at high speed and low power consumption is provided. Substrate potentials of P and N type transistors MP11 and MN11 constituting an inverter are controlled correspondingly to a stable state of the inverter. In a stable state of the inverter in which the P type transistor MP11 is ON, the substrate potential of the N type transistor MN11 which is OFF is lowered to ground potential or lower and, in a stable state of the inverter in which the N type transistor MN11 is ON, the substrate potential of the P type transistor MP11 which is OFF is raised to a power source potential or higher.
Claims10
A logic circuit comprising:
- an output node;
- a first transistor of a first conductivity type connected between a first power source and said output node;
- a second transistor of a second conductivity type connected between a second power source and said output node;
- an input node connected to control electrodes of said first and second transistors;
- a first control circuit for controlling a potential of a substrate of said first transistor in response to signals at said input node and output node without employing a potential of the signal at said output node;
- and
- a second control circuit for controlling a potential of a substrate of said second transistor in response to said signals on said input node and output node.
A logic circuit comprising:
- a first transistor of a first conductivity type connected between a first power source and an output node;
- a second transistor of a second conductivity type connected between a second power source and said output node;
- an input node connected to control electrodes of said first and second transistors;
- a first control circuit for supplying a potential different from a source potential of said second transistor to said substrate of said second transistor in response to said first transistor being in a conductive state and said second transistor being in a non-conductive state;
- and
- a second control circuit for supplying a potential different from a source potential of said first transistor to said substrate of said first transistor in response to said first transistor being in a non-conductive state and said second transistor being in a conductive state.
A logic circuit comprising:
- a first transistor of a first conductivity type connected between a first power source and an output node;
- a second transistor of a second conductivity type connected between a second power source and said output node;
- first control circuit for supplying a first potential different from a potential of said second power source to a substrate of said second transistor when a potential of said output node is substantially the same potential as said first power source;
- and
- second control circuit for supplying a second potential different from a potential of said first power source to a substrate of said first transistor when a potential of said output node is substantially the same potential as said second power source.
A logic circuit comprising:
- a first transistor of a first conductivity type connected between a first power source and an output node;
- a second transistor of a second conductivity type connected between a second power source and said output node;
- a third transistor of said first conductivity type connected between said first power source and a substrate of said first transistor;
- a fourth transistor of said second conductivity type connected between said second power source and a substrate of said second transistor;
- an input node connected to control electrodes of said first to fourth transistors;
- a fifth transistor of said first conductivity type connected between a third power source and said substrate of said first transistor and having a control electrode connected to said output node;
- and
- a sixth transistor of said second conductivity type connected between a fourth power source and said substrate of said second transistor and having a control electrode connected to said output node.
A logic circuit comprising:
- a first and second transistors of a first conductivity type connected in parallel between a first power source and an output node;
- a third and fourth transistors of a second conductivity type connected in series between a second power source and said output node;
- a fifth and sixth transistors of said first conductivity type connected in parallel between said first power source and at least one of substrates of said first and second transistors;
- a seventh and eighth transistors of said second conductivity type connected in series between said second power source and at least one of substrates of said third and fourth transistors;
- a first input node connected to control electrodes of said first, third, fifth and seventh transistors;
- a second input node connected to control electrodes of said second, fourth, sixth and eighth transistors;
- a ninth transistor of said first conductivity type connected between a third power source and at least one of said substrates of said first and second transistors and having a control electrode connected to said output node;
- and
- a tenth transistor of said second conductivity type connected between a fourth power source and at least one of said substrates of said third and fourth transistors and having a control electrode connected to said output terminal.
A logic circuit comprising a first power source, an output node, a transistor connected between said first power source and said output node, an input node connected to control electrode of said transistor, and a control circuit for controlling a potential of a substrate of said transistor in response to signals at said input node and output node without employing a potential of said output node as a potential of the substrate of said transistor.
A logic circuit comprising:
- a first power source;
- an output node;
- a resistor connected between said first power source and said output node;
- a first transistor connected between said output node and a second power source;
- a second transistor connected between a substrate of said first transistor and said second power source;
- an input node connected to control electrodes of said first and second transistors;
- and
- a third transistor connected between said substrate of said first transistor and said second power source and having a control electrode connected to said output node.
Dependencies are inferred from the claim text.