Programmable logic device with delay-locked loop

A method of preparing a programmable logic device to perform a desired logic function, the programmable logic device including a delay-locked loop, an array of configurable logic blocks that are programmably interconnected to each other and to programmable input/output blocks using a programmable interconnect matrix, the method comprising:

• a. providing a clock signal on a clock input terminal of the delay-locked loop;
• b. monitoring a lock terminal of the delay-locked loop for a lock signal;
• c. writing a set of configuration data into a plurality of configuration memory cells that collectively define the function and interconnection of the configurable logic blocks, interconnect matrix, and input/output blocks;
• and
• d. upon completion of (c), awaiting the lock signal before enabling the input/output blocks.

A programmable logic device comprising:

• a. means for synchronizing a first clock signal with a reference clock signal, wherein the synchronizing means produces a lock signal indicating that the first and reference clock signals are in phase;
• and
• b. a sequencer having:
• i. a sequencer input terminal adapted to receive the lock signal, wherein the sequencer is adapted to carry out a sequence of configuration steps that program the programmable logic device to perform a selected circuit operation;
• and
• ii. means for maintaining the programmable logic device in an inactive state until the sequencer receives the lock signal.