Techniques for programming programmable logic array devices

An apparatus to program a plurality of programmable logic devices (PLDs), comprising:

• a source configured to generate programming data;
• a second source to generate a clock signal;
• a first PLD device configured to receive the programming data and the clock signal, the first PLD device further configured to use the clock signal to clock in the programming data to program the first PLD device to a first logic state, the first PLD device further including a done circuit which is configured to generate a done signal when the first PLD device is programmed to the first logic state, wherein said first PLD device produces a predetermined status output signal when said first PLD device is ready to be programmed, and wherein said source configured to generate programming data and said second source are responsive to said status output signal by generating said programming data and said clock signal, respectively;
• and
• a second PLD device configured to receive the done signal, and in response thereto, is further configured to receive the clock signal and the programming data to program the second PLD device to a second logic state.

An apparatus to program a plurality of programmable logic devices (PLDs), comprising:

• a source configured to generate programming data;
• a second source to generate a clock signal;
• a first PLD device configured to receive the programming data and the clock signal, the first PLD device further configured to use the clock signal to clock in the programming data to program the first PLD device to a first logic state, the first PLD device further including a done circuit which is configured to generate a done signal when the first PLD device is programmed to the first logic state, wherein said first PLD device produces a predetermined condone output signal until said first PLD device is fully programmed, and wherein said source configured to generate programming data and said second source are responsive to said condone output signal by being enabled to generate said programming data and said clock signal, respectively, by said condone output signals;
• and
• a second PLD device configured to receive the done signal, and in response thereto, is further configured to receive the clock signal and the programming data to program the second PLD device to a second logic state.

An apparatus to program a plurality of programmable logic devices (PLDs), comprising:

• a source configured to generate programming data;
• a second source to generate a clock signal;
• a first PLD device configured to receive the programming data and the clock signal, the first PLD device further configured to use the clock signal to clock in the programming data to program the first PLD device to a first logic state, the first PLD device further including a done circuit which is configured to generate a done signal when the first PLD device is programmed to the first logic state, wherein said first PLD device is responsive to a configuration signal by preparing itself to be re-programmed by said source configured to generate programming data, wherein said first PLD produces a predetermined condone output signal until said first PLD device is fully programmed, wherein said source configured to generate programming data and said second source are responsive to said condone output signal by being enabled to generate said programming data and said clock signal, respectively, by said condone output signal, and wherein said first PLD device produces said condone signal in response to said configuration signal;
• and
• a second PLD device configured to receive the done signals and in response thereto, is further configured to receive the clock signal and the programming data to program the second PLD device to a second logic state.

A programmable logic device, comprising:

• a data input port configured to receive programming data;
• a clock port configured to receive a clock signal;
• programmable logic circuitry, coupled to the data input port, the programmable logic circuitry being configured to be programmed in response to the programming data and the clock signal received at the programmable logic device
• a program enable circuit, coupled to the programmable logic circuitry, and configured to selectively enable the programmable logic circuitry to be programmed by the programming data when the program enable circuit receives an enable signal;
• a done circuit, coupled to the programming logic, the done circuit being configured to generate a done signal when the programming data has programmed the programmable logic circuitry to a first logic state;
• and
• a condone circuit for producing a predetermined condone output signal until said device is fully programmed.

A programmable logic device, comprising:

• a data input port configured to receive programming data;
• a clock port configured to receive a clock signal;
• programmable logic circuitry, coupled to the data input port, the programmable logic circuitry being configured to be programmed in response to the programming data and the clock signal received at the programmable logic device;
• a program enable circuit, coupled to the programmable logic circuitry, and configured to selectively enable the programmable logic circuitry to be programmed by the programming data when the program enable circuit receives an enable signal;
• a done circuit, coupled to the programming logic, the done circuit being configured to generate a done signal when the programming data has programmed the programmable logic circuitry to a first logic state;
• and
• a condone signal sensing circuit for sensing the level of a condone signal external to said device and for preparing said device to begin normal operation as a logic device when said condone signal has a predetermined level.

A programmable logic device, comprising:

• a data input port configured to receive programming data;
• a clock port configured to receive a clock signal;
• programmable logic circuitry, coupled to the data input port, the programmable logic circuitry being configured to be programmed in response to the programming data and the clock signal received at the programmable logic device
• a program enable circuit, coupled to the programmable logic circuitry, and configured to selectively enable the programmable logic circuitry to be programmed by the programming data when the program enable circuit receives an enable signal;
• a done circuit, coupled to the programming logic, the done circuit being configured to generate a done signal when the programming data has programmed the programmable logic circuitry to a first logic state;
• and
• a configuration signal sensing circuit for sensing the level of a configuration signal external to said device and for preparing said device to be re-programmed when said configuration signal has a predetermined level.