Method of forming planarized multilevel metallization in an integrated circuit

A planarized multilevel metallization region of an integrated circuit, comprising:

• a substrate having a plurality of active regions at a first surface of the substrate;
• a dielectric layer disposed over a portion of the substrate having an opening therethrough exposing a portion of at least one of the plurality of active regions;
• a conductive plug in the opening in the dielectric layer disposed over the exposed portion of the active region;
• a plurality of planar interconnect lines;
• the interconnect lines comprising:
• aluminum conductive lines;
• a first glue layer disposed under the aluminum conductive lines;
• a second glue layer disposed over the aluminum conductive lines;
• a first etch stop layer disposed over the second glue layer;
• wherein at least one of the plurality of interconnect lines is disposed over the tungsten plug;
• a plurality of first insulating regions disposed between the interconnect lines and disposed over the dielectric layer and a portion of the interconnect lines exposing an upper surface of a portion of the interconnect lines;
• a plurality of planar conductive pillars disposed over selected portions of the interconnect lines;
• the pillars comprising:
• an aluminum layer;
• a third glue layer disposed over the aluminum layer;
• a second etch stop layer disposed over the third glue layer;
• a plurality of second planar insulating regions disposed between the conductive pillars and disposed over the first insulating regions and the exposed portions of the interconnect lines.