Semiconductor chip carrier having partially buried conductive pattern and semiconductor device using the same

A semiconductor device comprising:

• a semiconductor chip having a plurality of internal circuit components forming an electric circuit and having a plurality of conductive contacts on a lower surface for external mounting and electrical connection of said semiconductor chip;
• a semiconductor chip carrier for mounting and electrically connecting said semiconductor chip, said chip carrier comprising an insulating layer having a major surface and a reverse surface,
• said major surface comprising a mounting area, an outer peripheral area, and an inner peripheral area,
• said mounting area being located on one end of said major surface for mounting said semiconductor chip, and having a perimeter defined by projections of sides of said semiconductor chip onto said mounting area,
• said outer peripheral area being located at an opposite end of said major surface outside of said mounting area and having a plurality of through holes open to said major surface and to said reverse surface, and
• said inner peripheral area being located intermediate to said mounting area and said outer peripheral area;
• a conductive pattern in contact with said insulating layer, said conductive pattern comprising a plurality of conductive pads, a plurality of vertical conductive interconnects, and a plurality of circuit sub-patterns,
• said plurality of conductive pads being located in said mounting area for aligning with and bonding to associated conductive contacts of said plurality of conductive contacts such that each of said plurality of conductive pads correspoends to a location of one of said associated conductive contacts, and defining positions within said mounting area of a plurality of connections between said plurality of conductive pads and said plurality of conductive contacts, wherein said mounting area within said perimeter of said semiconductor chip is substantially free of conductive material intermediate said semiconductor chip and said major surface other than said plurality of connections,
• said plurality of vertical conductive interconnects passing through and filling said plurality of through holes, and providing a plurality of surface electrical contacts located on each of said outer peripheral area and said reverse surface,
• said plurality of circuit sub-patterns each electrically connecting an associated one of said plurality of conductive pads to an associated one of said plurality of vertical conductive interconnects;
• and
• a sealant layer comprising a single material and completely filling a space defined between said lower surface and said perimeter of said mounting area, and completely surrounding said plurality of connections, said sealant layer being free of voids within said space, whereby heat transfer between said semiconductor chip and said chip carrier is improved, and cracking of said plurality of connections is reduced.