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US 6,191,472 B1Granted
Hole geometry of a semiconductor package substrate
AssigneeIntel Corporation
InventorMohiuddin M. Mazumder
Life of this patent
Estimating the term…
Abstract
A semiconductor package substrate includes at least one insulative layer, at least two metal lines next to one another on a first side of the insulative layer, and a first metal layer on a second side of the insulative layer opposing the first side. An opening is formed in the first metal layer in an area between the metal lines. Two lands remain part of the first metal layer. The lands are located adjacent the opening and each land opposes a respective one of the metal lines located next to one another.
Claims19
A semiconductor package substrate comprising:
- at least a first insulative layer;
- at least two metal lines located next to one another in a first plane on one side of the insulative layer;
- a first metal layer, in a second plane substantially parallel to and spaced from the first plane, on a side of the insulative layer opposing the metal lines, the first metal layer having at least one opening, being entirely bounded by the first metal layer, formed therein in an area between the metal lines while leaving two respective lands adjacent the opening, each land opposing a respective one of the metal lines located next to one another so as to ensure that a signal in a respective line travels in a path substantially parallel to a signal in a respective land;
- and
- at least a second insulative layer on a side of the first metal layer opposing the first insulative layer and covering the opening, the opening providing space for outgassing from at least one of the insulative layers into the opening.
2 more elements
A semiconductor package comprising:
- a package substrate having at least a first insulative layer, at least two metal lines located next to one another in a first plane on one side of the insulative layer, a first metal layer, in a second plane substantially parallel to and spaced from the first plane, on a side of the insulative layer opposing the metal lines, the first metal layer having at least one opening, being entirely bounded by the first metal layers, formed therein in an area between the metal lines while leaving two respective lands adjacent the opening, each land opposing a respective one of the metal lines located next to one another so as to ensure that a signal in a respective line travels in a path substantially parallel to a signal in a respective land, and at least a second insulative layer on a side of the first metal layer opposing the first insulative layer and covering the opening, the opening providing space for outgassing from at least one of the insulative layers into the opening;
- and
- a first integrated circuit mounted on the substrate and electrically connected to the metal lines and the first metal layer.
A semiconductor package comprising:
- a package substrate having an insulative layer, at least two metal lines located next to one another on a first side of the insulative layer, and a first metal layer on a second side of the insulative layer opposing the first side, the first metal layer having at least one opening, completely bounded by the first metal layer, formed therein in an area between the metal lines while leaving two respective lands adjacent the opening, each land opposing a respective one of the metal lines located next to one another;
- a first integrated circuit mounted to the substrate and electrically connected to the metal lines and the first metal layer, the first integrated circuit comprising a first electrical element which is connected to a first of the metal lines and to the metal layer, and a second electrical element which is connected to a second of the metal lines and to the metal layer;
- and
- a second integrated circuit mounted to the substrate and electrically connected to the metal lines and the metal layer, the second integrated circuit comprising a third electrical element which is connected to the first metal line and to the metal layer, and a fourth electrical element which is connected to the second metal line and the metal layer, the first electrical element switching the third electrical element and the second electrical element switching the fourth electrical element, the opening being located between the first integrated circuit and the second integrated circuit.
1 more element
Dependencies are inferred from the claim text.