Nitride-oxide sidewall spacer for salicide formation

A MOSFET device structure featuring a metal silicide-polysilicon, polycide gate structure and a composite silicon nitride-silicon oxide spacer, with the top of the composite spacer terminating at the center of a side of the metal silicide component of the polycide gate structure, comprising:

• field oxide regions on the surface of a semiconductor substrate;
• a device region between said field oxide regions;
• said polycide gate structure, comprised of a first metal silicide layer on a narrow, polysilicon gate structure, between about 500 to 2000 Angstroms in width, overlying a gate insulator layer, on said semiconductor substrate, in the center of said device region;
• a first insulator spacer, comprised of silicon oxide, on the sides of said polycide structure, with the bottom of said first insulator spacer directly overlying only the entire first portion of the surface of said semiconductor substrate, with said first portion of the surface of said semiconductor substrate comprised of a lightly doped source/drain region, incorporating arsenic or phosphorous ions at a dose between about 1E11 to 1E14 atoms/cm2 with a width between about 200 to 5000 Angstroms, extending from the sides of said polysilicon gate structure, and with said lightly doped source/drain region terminating at a first depth in said semiconductor substrate, and with the top of said first insulator spacer terminating at the center of the side of said first metal silicide layer on said polysilicon gate structure;
• a second insulator spacer, comprised of silicon nitride, located on the sides of said first insulator spacer, and with the bottom of said second insulator spacer directly overlying only the entire second portion of the surface of said semiconductor substrate, where said second portion of the surface of said semiconductor substrate is comprised with a medium doped source/drain region, with a width between about 200 to 5000 Angstroms, extending from the edge of said first portion, or said lightly doped source/drain region and with said medium doped source/drain region terminating at a second depth in said semiconductor substrate, with said second depth greater in depth than said first depth, and with the top of said second insulator spacer located at the same height as said first insulator spacer;
• a third portion of the surface of said semiconductor substrate, located between the edge of said second insulator spacer, or located at the edge of said medium doped source/drain region, and a field oxide region, and comprised with a heavily doped source/drain region, and with said heavily doped source/drain region terminating at a third depth in said semiconductor substrate, with said third depth greater in depth than said second depth;
• a second metal silicide layer on the top surface of said third portion of the surface of said semiconductor substrate;
• and
• a metal contact structure, overlying and contacting, a portion of said second metal silicide layer.