SOI based transistor having an independent substrate potential control
AssigneeKabushiki Kaisha Toshiba
InventorTomoaki Shino
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Abstract
A semiconductor device comprises a semiconductor layer formed on an insulation layer, a pair of source and drain diffusion layer formed on a surface of the semiconductor layer, a first gate electrode disposed on the semiconductor layer region interposed between the pair of source and drain diffusion layer through a gate insulation film, a substrate potential control layer coupled to the semiconductor layer in a region interposed between the pair of the source and drain diffusion layer and formed in such a manner that the first gate electrode does not exist thereon, and a second gate electrode disposed to be in contact with the first gate electrode.
Claims10
A semiconductor device comprising:
- a semiconductor layer formed on an insulation layer;
- a source diffusion layer and a drain diffusion layer formed in said semiconductor layer, said source diffusion layer and said drain diffusion layer being in contact with said insulation layer;
- a first gate electrode disposed on a gate insulation film over a first region of said semiconductor located between said source diffusion layer and said drain diffusion layer, said first gate electrode having a bottom surface area substantially equal to an upper surface area of said first region;
- a substrate potential control layer coupled to said first region and having a portion formed in a second region of said semiconductor layer that is not under said first gate electrode;
- and
- a second gate electrode disposed on and in contact with said first gate electrode.
A semiconductor device comprising:
- a semiconductor layer formed on an insulation layer;
- a first gate electrode formed on a gate insulation layer over a first region of said semiconductor layer;
- a source diffusion layer and a drain diffusion layer formed in said semiconductor layer so as to be on opposite sides of said first region under said first gate electrode;
- and
- a substrate potential control layer coupled to said first region and having a portion adjacent to said first region whose length runs parallel to a line running between said source diffusion layer and said drain diffusion layer and is equal to a length of said first gate electrode running parallel to a line between said source diffusion layer and said drain diffusion layer.
A semiconductor device comprising:
- a semiconductor layer formed on an insulation layer;
- a gate electrode disposed on a gate insulation film over a first region of said semiconductor layer, said first gate electrode having a bottom surface area substantially equal to an upper surface area of said first region;
- a source diffusion layer and a drain diffusion layer formed in said semiconductor layer on each of two opposite sides of said gate electrode to interpose said gate electrode and said first region there between;
- a substrate potential control layer coupled to said first region;
- and
- a conductor formed on a region of said substrate potential control layer and coupled to said gate electrode.
A semiconductor device comprising:
- a semiconductor layer formed on an insulation layer;
- a source diffusion layer and a drain diffusion layer formed in said semiconductor layer;
- a first gate electrode disposed on a gate insulation film over a first region of said semiconductor layer located between said source diffusion layer and said drain diffusion layer, said first gate electrode having a bottom surface area substantially equal to an upper surface area of said first region;
- a substrate potential control layer coupled to said first region and having at least a portion formed in a second region of said semiconductor layer that is not under said first gate electrode;
- and
- a second gate electrode disposed in contact with said first gate electrode and coupled directly or through a conductive material to said substrate potential control layer.
A method of manufacturing a semiconductor device having a semiconductor layer formed on an insulation layer, a first gate electrode disposed on a gate insulation layer over a first region of semiconductor layer, a source diffusion layer and a drain diffusion layer formed in said semiconductor layer on each of two opposite sides of said first gate electrode, a substrate potential control layer coupled to said first region, and a second gate electrode disposed to be in contact with said first gate electrode, comprising the steps of:
- forming said first electrode;
- forming a conductive film on the overall surface in such a manner that said conductive film in contact with said first gate electrode so as to serve as said second gate electrode;
- forming a mask pattern on said conductive film;
- forming said second gate electrode by transferring said mask pattern to said conductive film;
- and
- forming said substrate potential control layer by transferring the pattern of said second gate electrode to said semiconductor layer.
Dependencies are inferred from the claim text.