DRAM memory with TFT superposed on a trench capacitor
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorJiro Matsufusa
Life of this patent
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Abstract
In order to correspond to high integration with large capacity of a semiconductor device, provided are a structure of the semiconductor device and a method for manufacturing the same in which a horizontal dimension can be reduced in either a memory cell region or a region where a peripheral circuit is to be formed or both the regions. A TFT is superposed on a trench capacitor with an insulation film provided therebetween in a DRAM memory cell region, and a TFT is superposed on a bulk transistor with an insulation film provided therebetween in a region where a peripheral circuit is to be formed. Consequently, elements are arranged three-dimensionally. Thus, a horizontal dimension of a region where each element is to be formed can be reduced.
Claims10
A semiconductor device comprising:
- a trench capacitor provided in a semiconductor substrate for constituting a memory cell, the trench capacitor having a plurality of electrodes, one of the electrodes being a storage node;
- an insulation film provided on said trench capacitor;
- and
- a thin film transistor provided on said insulation film,
- wherein said thin film transistor is provided in such a manner that at least a part thereof is superposed on said trench capacitor, said thin film transistor having a source/drain region electrically connected to the storage node through a contact provided solely in said insulation film interposed therebetween.
A semiconductor device comprising:
- a memory cell region;
- and
- a peripheral circuit region coupled to the memory cell region, the peripheral circuit region comprising,
- a MOS transistor having a gate electrode and a source/drain region, said source/drain region being provided in a semiconductor substrate,
- an isolation region provided in said semiconductor substrate,
- a first insulation film provided on at least one of said MOS transistor and said isolation region, and
- a first thin film transistor provided on said first insulation film,
- wherein said first thin film transistor is provided in such a manner that at least a part thereof is superposed on at least one of said MOS transistor and said isolation region.
Dependencies are inferred from the claim text.